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32 Open 909 Closed
32 Open 909 Closed
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Issues list

Adding rule for generic type in generic port enhancement
#1402 opened Feb 11, 2025 by PelleEikeberg
1
Error when accessing record elements of a vhdl-2008 referenced record. bug
#1399 opened Jan 22, 2025 by masubious
1
@jeremiah-c-leary
3
Mention of VSG in an FPGA presentation question
#1398 opened Jan 21, 2025 by lgu-appear
@jeremiah-c-leary
5
Whitespace rules for file declarations and file type definitons enhancement
#1397 opened Jan 19, 2025 by JHertz5
1
Blank line rules for case generate statements enhancement
#1391 opened Jan 17, 2025 by JHertz5
Improve consistent case rules to work in package files enhancement
#1384 opened Jan 1, 2025 by JHertz5
Create a rule to align when keywords in selected assignments enhancement
#1374 opened Dec 22, 2024 by JHertz5
2
Add indent and blank line rules for subprogram instantiation declarations enhancement
#1365 opened Dec 21, 2024 by JHertz5
1
@JHertz5
3
Add option for custom error messages enhancement
#1358 opened Dec 20, 2024 by PelleEikeberg
1
@jeremiah-c-leary
11
Rules to enforce case on the shared keyword in a shared variable declaration enhancement
#1289 opened Oct 22, 2024 by urbite
@urbite
5
Alignment incorrect for range declarations of unconstrained record elements spread over multiple lines bug
#1250 opened Oct 15, 2024 by obruendl
2
@JHertz5
7
if_009 with smart tabs indentation wrong output bug
#1218 opened Aug 26, 2024 by magborresen
1
@jeremiah-c-leary
2
Extend concurrent_009 to comment in between multiline condition enhancement
#1213 opened Aug 23, 2024 by Anselmo95
@jeremiah-c-leary
3
record element is incorrectly recognized as type element bug
#1187 opened Jul 1, 2024 by mattdominik
@jeremiah-c-leary
6
Multiple local_rule Directories enhancement
#1175 opened Jun 7, 2024 by Benito-E
@jeremiah-c-leary
5
Local Rule Creation Documentation question
#1174 opened Jun 3, 2024 by Benito-E
@jeremiah-c-leary
5
pytest occasionally reports an issue but does not fail bug
#1157 opened Mar 28, 2024 by jeremiah-c-leary
@jeremiah-c-leary
Enable pylint in project enhancement
#1148 opened Mar 24, 2024 by alonbl
@jeremiah-c-leary
Consider removing vsg/rules/__init__.py and vsg/vhdlFile/extract/__init__.py import index files enhancement Version 4.0 Rewrite
#1147 opened Mar 24, 2024 by alonbl
@jeremiah-c-leary
Rename signal as they are defined enhancement
#1040 opened Nov 1, 2023 by ungultig1
6
Collaboration proposal question
#920 opened Feb 23, 2023 by kraigher
@jeremiah-c-leary
4
Refactoring classify process to pass object enhancement
#881 opened Nov 21, 2022 by jeremiah-c-leary
@jeremiah-c-leary
Extra prefix/suffix rules for package contents
#690 opened Nov 19, 2021 by imd1
@jeremiah-c-leary
3
Resiliance to malformed VHDL useability
#669 opened Nov 9, 2021 by imd1
@jeremiah-c-leary
2
Rule to remove superfluous brackets
#617 opened Oct 6, 2021 by imd1
@jeremiah-c-leary
4
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