Skip to content

Pull requests: jeremiah-c-leary/vhdl-style-guide

New pull request New
7 Open 441 Closed
7 Open 441 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Issue 1218
#1401 opened Jan 25, 2025 by jeremiah-c-leary Loading…
1
Issue#1399: external names would end processing of the name production.
#1400 opened Jan 22, 2025 by jeremiah-c-leary Loading…
1
Issue#1358: Adding user_error_message option.
#1387 opened Jan 4, 2025 by jeremiah-c-leary Loading…
1
Issue#1365: Added blank line and indent rules for subprogram instantiation declarations
#1379 opened Dec 29, 2024 by JHertz5 • Draft
1
Issue#1250: Corrected alignment of multiline variable and signal declarations for align_left = no
#1345 opened Dec 11, 2024 by JHertz5 Loading…
1
3
Tag "productions" to allow using VSG as a VHDL parser
#1309 opened Nov 3, 2024 by jfcliche Loading…
@jfcliche
1
Add rules to require **begin** keyword for generate statements enhancement
#1240 opened Oct 6, 2024 by larshb Loading…
@larshb
4
ProTip! Type g i on any issue or pull request to go back to the issue listing page.