add DatPath module template and a complete 9-inst ALU with more circu…

…its-like description

.gitignore

@@ -1,7 +1,7 @@
 *.class
 *.log
 .DS_Store
-.graffle
+*.graffle
 
 # sbt specific
 .cache

src/main/scala/SingleCycle/ALU.scala

@@ -66,4 +66,47 @@ class ALU extends Module {
 // SUB, ADD, AND, OR, and SLT, BEQ in ALU operations
 //---------------------------------------------------//
 
+object ALU9
+{
+	def FN_AND	= 0.U(3.W)	//000
+	def FN_OR	= 1.U(3.W)	//001
+	def FN_ADD	= 2.U(3.W)	//010
+	def FN_SUB	= 6.U(3.W)	//110
+	def FN_SLT	= 7.U(3.W)	//111
 
+	def FN_BEQ	= FN_SUB	//011
+
+	//def isSub(cmd: UInt) = cmd(6)
+	def isSub(cmd: UInt) = cmd === FN_SUB || cmd === FN_SLT
+}
+import ALU9._
+
+class ALU9 extends Module{
+	val io = IO(new Bundle{
+		val in1		= Input(UInt(32.W))
+		val in2 	= Input(UInt(32.W))
+		val ALUctr 	= Input(UInt(3.W))
+		val ALUout	= Output(UInt(32.W))
+		val cmp_out	= Output(Bool())
+		})
+
+	//val SIntA = SInt(32.W)
+	//val SIntB = SInt(32.W)
+
+	// ADD, SUB
+	val in2_inv = Mux(isSub(io.ALUctr), ~io.in2, io.in2)
+	val in1_xor_in2 = io.in1 ^ in2_inv
+	val adder_out = io.in1 + in2_inv + isSub(io.ALUctr)
+
+	// SLT and BEQ comparation Output
+	io.cmp_out := Mux(io.ALUctr === FN_BEQ, in1_xor_in2 === 0.U, 
+		Mux(io.in1(31) != io.in2(31), adder_out(31),
+		Mux(adder_out(31), true.B, false.B)))
+
+	// AND, OR, however this can also output XOR
+  val logic_out = Mux(io.ALUctr === FN_OR, in1_xor_in2, 0.U) | 
+  Mux(io.ALUctr === FN_OR || io.ALUctr === FN_AND, io.in1 & io.in2, 0.U)
+  val out = Mux(io.ALUctr === FN_ADD || io.ALUctr === FN_SUB, adder_out, logic_out)
+
+  io.ALUout := out
+}

src/main/scala/SingleCycle/DatPath.scala

@@ -0,0 +1,41 @@
+//**************************************************************************
+//--------------------------------------------------------------------------
+// ercesiMIPS Single Cycle Processor Data path
+//
+// Meng zhang
+// version 0.1
+//--------------------------------------------------------------------------
+//**************************************************************************
+
+package SingleCycle
+
+import chisel3._
+import chisel3.util._
+//import chisel3.iotesters.Driver
+//import utils.ercesiMIPSRunner
+class DatToCtlIo extends Bundle()
+{
+	val cmp_out = Output(Bool())
+	//val Imm32	= Output(UInt(32.W))
+	//val nPC_sel	= Output(Bool())
+}
+
+class DPathIo extends Bundle()
+{
+	//val host		= new HTIFIO()
+	val imem_addr	= Output(UInt(32.W))
+	val dmem_addr	= Output(UInt(32.W))
+	val dmem_datIn	= Output(UInt(32.W))
+	val dmem_datOut	= Input(UInt(32.W))
+	val ctl  		= new CtltoDatIo().flip()
+	val dat  		= new DatToCtlIo()
+}
+
+class DatPath extends Module {
+	val io = IO(new DPathIo ())
+
+	val alu9 = Module(new ALU9())
+	//
+	// add your code
+	// 
+}