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De-uniquify hierarchical blocks in genus for hierarchical flows #812

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merged 4 commits into from
Oct 23, 2023
Merged

De-uniquify hierarchical blocks in genus for hierarchical flows #812

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2d77545
De-uniquify hierarchical blocks in genus for hierarchical flows
jerryz123 Oct 22, 2023
fa1373b
Only de-uniquify for DDI versions >= 211
jerryz123 Oct 22, 2023
d9440af
Add warning messages when de-uniquifying in genus
jerryz123 Oct 22, 2023
dc017b2
change_link should copy_attributes of the uniquified instance
jerryz123 Oct 22, 2023
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15 changes: 14 additions & 1 deletion hammer/synthesis/genus/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

from hammer.vlsi import HammerTool, HammerToolStep, HammerToolHookAction, HierarchicalMode
from hammer.utils import VerilogUtils
from hammer.vlsi import HammerSynthesisTool
from hammer.vlsi import HammerSynthesisTool, PlacementConstraintType
from hammer.logging import HammerVLSILogging
from hammer.vlsi import MMMCCornerType
import hammer.tech as hammer_tech
Expand Down Expand Up @@ -302,6 +302,19 @@ def syn_generic(self) -> bool:
# Clock mapping needs at least the attributes cts_inverter_cells and cts_logic_cells to be set
self.append("set_db map_clock_tree true")
self.verbose_append("syn_generic")

# With DDI, hierarchical instances may be uniquified. Use change_link to deuniquify them
if self.hierarchical_mode.is_nonleaf_hierarchical() and self.version() >= self.version_number("211"):
pcs = list(filter(lambda c: c.type == PlacementConstraintType.Hierarchical, self.get_placement_constraints()))
for pc in pcs:
self.append("""
# Attempt to deuniquify hinst:{inst}, incase it was uniquified
set uniquified_name [get_db hinst:{inst} .module.name]
if {{ $uniquified_name ne \"{master}\" }} {{
puts [format \"WARNING: instance hinst:{inst} was uniquified to be an instance of $uniquified_name, not {master}. Attempting to fix\"]
change_link -copy_attributes -instances {{{inst}}} -design_name module:{top}/{master}
}}""".format(inst=pc.path, top=self.top_module, master=pc.master))

return True

def syn_map(self) -> bool:
Expand Down