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Added Xcvmem
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Signed-off-by: Jessica Mills <[email protected]>

CV32E40Pv2 Update Post Increment Load/Store

    Removed redundant instructions for all CORE-V Post Increment Load/Store
    as this duplicates RISC-V Load/Store instructions.

    * opcodes/riscv-opc.c: Removed redundant CORE-V Post Increment
      Load/Store instructions.
    * gas/testsuite/gas/riscv/cv-mem-lb.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lb.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lbu.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lbu.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lh.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lh.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lhu.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lhu.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lw.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lw.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sb.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sb.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sh.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sh.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sw.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sw.s: deleted.

Signed-off-by: Nandni Jamnadas <[email protected]>

Changed post inc instructions mnemonic

For issue [#101](#101)

Files Changed:

  * opcodes/riscv-opc.c: Changed instruction mnemonic.
  * gas/testsuite/gas/riscv/cv-mem-fail-march.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-march.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbrrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbupost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lbupost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lburrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lburrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhrrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhupost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhupost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhurrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lhurrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lwpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lwpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lwrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-lwrrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-sbpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-sbpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-sbrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-sbrrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-shpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-shpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-shrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-shrrpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-swpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-swpost.s: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-swrrpost.d: Likewise.
  * gas/testsuite/gas/riscv/cv-mem-swrrpost.s: Likewise.

Signed-off-by: Mary Bennett <[email protected]>
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jessicamills authored and Mary Bennett committed Oct 2, 2023
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5 changes: 5 additions & 0 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1392,6 +1392,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvhwlp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
Expand Down Expand Up @@ -2596,6 +2597,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVHWLP:
return riscv_subset_supports (rps, "xcvhwlp");
case INSN_CLASS_XCVMEM:
return riscv_subset_supports (rps, "xcvmem");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
Expand Down Expand Up @@ -2842,6 +2845,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xcvalu";
case INSN_CLASS_XCVHWLP:
return "xcvhwlp";
case INSN_CLASS_XCVMEM:
return "xcvmem";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
Expand Down
14 changes: 14 additions & 0 deletions gas/ChangeLog.COREV
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@@ -1,3 +1,17 @@
2021-08-06 Enrico Tabanelli <[email protected]>

* config/tc-riscv.c (riscv_multi_subset_supports): Add
post-increment and register-indexed load/store instruction
class.
(validate_riscv_insn, riscv_ip): Add post-increment symbol.
* doc/c-riscv.texi: Added details on CORE-V post-incrementing
and reg-reg load/store ops ISA options.

2021-01-27 Jessica Mills <[email protected]>

* config/tc-riscv.c (md_apply_fix): Remove unnecessary overflow check
for BFD_RELOC_RISCV_CVPCREL_UI12 & BFD_RELOC_RISCV_CVPCREL_URS1.

2021-08-23 Jessica Mills <[email protected]>

* config/tc-riscv.c (riscv_ip): Fix boundary bug for hardware loop
Expand Down
2 changes: 2 additions & 0 deletions gas/config/tc-riscv.c
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Expand Up @@ -1369,6 +1369,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case ',': break;
case '(': break;
case ')': break;
case '!': break;
case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break; /* Macro operand, must be symbol. */
Expand Down Expand Up @@ -3161,6 +3162,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case ')':
case '[':
case ']':
case '!':
if (*asarg++ == *oparg)
continue;
break;
Expand Down
5 changes: 5 additions & 0 deletions gas/doc/c-riscv.texi
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Original file line number Diff line number Diff line change
Expand Up @@ -760,6 +760,11 @@ The Xcvhwlp extension provides instructions for hardware loop operations.

It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}

@item Xcvmem
The Xcvmem extension provides instructions for post inc load/store operations.

It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}

@item XTheadBa
The XTheadBa extension provides instructions for address calculations.

Expand Down
93 changes: 93 additions & 0 deletions gas/testsuite/ChangeLog.COREV
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Original file line number Diff line number Diff line change
@@ -1,3 +1,96 @@
2021-08-06 Enrico Tabanelli <[email protected]>

* gas/riscv/cv-mem-fail-operand-01.d: Add post-increment
and register-indexed load/store test.
* gas/riscv/cv-mem-fail-operand-01.s: Likewise.
* gas/riscv/cv-mem-fail-operand-01.l: Likewise.
* gas/riscv/cv-mem-fail-operand-02.d: Likewise.
* gas/riscv/cv-mem-fail-operand-02.s: Likewise.
* gas/riscv/cv-mem-fail-operand-02.l: Likewise.
* gas/riscv/cv-mem-fail-operand-03.d: Likewise.
* gas/riscv/cv-mem-fail-operand-03.s: Likewise.
* gas/riscv/cv-mem-fail-operand-03.l: Likewise.
* gas/riscv/cv-mem-fail-operand-04.d: Likewise.
* gas/riscv/cv-mem-fail-operand-04.s: Likewise.
* gas/riscv/cv-mem-fail-operand-04.l: Likewise.
* gas/riscv/cv-mem-fail-operand-05.d: Likewise.
* gas/riscv/cv-mem-fail-operand-05.s: Likewise.
* gas/riscv/cv-mem-fail-operand-05.l: Likewise.
* gas/riscv/cv-mem-fail-march.d: Likewise.
* gas/riscv/cv-mem-fail-march.s: Likewise.
* gas/riscv/cv-mem-fail-march.l: Likewise.
* gas/riscv/cv-mem-lb.d: Likewise.
* gas/riscv/cv-mem-lbpost.d: Likewise.
* gas/riscv/cv-mem-lbpost.s: Likewise.
* gas/riscv/cv-mem-lbrr.d: Likewise.
* gas/riscv/cv-mem-lbrrpost.d: Likewise.
* gas/riscv/cv-mem-lbrrpost.s: Likewise.
* gas/riscv/cv-mem-lbrr.s: Likewise.
* gas/riscv/cv-mem-lb.s: Likewise.
* gas/riscv/cv-mem-lbu.d: Likewise.
* gas/riscv/cv-mem-lbupost.d: Likewise.
* gas/riscv/cv-mem-lbupost.s: Likewise.
* gas/riscv/cv-mem-lburr.d: Likewise.
* gas/riscv/cv-mem-lburrpost.d: Likewise.
* gas/riscv/cv-mem-lburrpost.s: Likewise.
* gas/riscv/cv-mem-lburr.s: Likewise.
* gas/riscv/cv-mem-lbu.s: Likewise.
* gas/riscv/cv-mem-lh.d: Likewise.
* gas/riscv/cv-mem-lhpost.d: Likewise.
* gas/riscv/cv-mem-lhpost.s: Likewise.
* gas/riscv/cv-mem-lhrr.d: Likewise.
* gas/riscv/cv-mem-lhrrpost.d: Likewise.
* gas/riscv/cv-mem-lhrrpost.s: Likewise.
* gas/riscv/cv-mem-lhrr.s: Likewise.
* gas/riscv/cv-mem-lh.s: Likewise.
* gas/riscv/cv-mem-lhu.d: Likewise.
* gas/riscv/cv-mem-lhupost.d: Likewise.
* gas/riscv/cv-mem-lhupost.s: Likewise.
* gas/riscv/cv-mem-lhurr.d: Likewise.
* gas/riscv/cv-mem-lhurrpost.d: Likewise.
* gas/riscv/cv-mem-lhurrpost.s: Likewise.
* gas/riscv/cv-mem-lhurr.s: Likewise.
* gas/riscv/cv-mem-lhu.s: Likewise.
* gas/riscv/cv-mem-lw.d: Likewise.
* gas/riscv/cv-mem-lwpost.d: Likewise.
* gas/riscv/cv-mem-lwpost.s: Likewise.
* gas/riscv/cv-mem-lwrr.d: Likewise.
* gas/riscv/cv-mem-lwrrpost.d: Likewise.
* gas/riscv/cv-mem-lwrrpost.s: Likewise.
* gas/riscv/cv-mem-lwrr.s: Likewise.
* gas/riscv/cv-mem-lw.s: Likewise.
* gas/riscv/cv-mem-march-rv32i-xcorev.d: Likewise.
* gas/riscv/cv-mem-march-rv32i-xcorev.s: Likewise.
* gas/riscv/cv-mem-sb.d: Likewise.
* gas/riscv/cv-mem-sbpost.d: Likewise.
* gas/riscv/cv-mem-sbpost.s: Likewise.
* gas/riscv/cv-mem-sbrr.d: Likewise.
* gas/riscv/cv-mem-sbrrpost.d: Likewise.
* gas/riscv/cv-mem-sbrrpost.s: Likewise.
* gas/riscv/cv-mem-sbrr.s: Likewise.
* gas/riscv/cv-mem-sb.s: Likewise.
* gas/riscv/cv-mem-sh.d: Likewise.
* gas/riscv/cv-mem-shpost.d: Likewise.
* gas/riscv/cv-mem-shpost.s: Likewise.
* gas/riscv/cv-mem-shrr.d: Likewise.
* gas/riscv/cv-mem-shrrpost.d: Likewise.
* gas/riscv/cv-mem-shrrpost.s: Likewise.
* gas/riscv/cv-mem-shrr.s: Likewise.
* gas/riscv/cv-mem-sh.s: Likewise.
* gas/riscv/cv-mem-sw.d: Likewise.
* gas/riscv/cv-mem-swpost.d: Likewise.
* gas/riscv/cv-mem-swpost.s: Likewise.
* gas/riscv/cv-mem-swrr.d: Likewise.
* gas/riscv/cv-mem-swrrpost.d: Likewise.
* gas/riscv/cv-mem-swrrpost.s: Likewise.
* gas/riscv/cv-mem-swrr.s: Likewise.
* gas/riscv/cv-mem-sw.s: Likewise.

2021-01-27 Jessica Mills <[email protected]>

* gas/riscv/cv-hwlp-fail-operand-07.l: Remove obsolete
BFD_RELOC_RISCV_CVPCREL_UI12 overflow error message.

2021-08-23 Jessica Mills <[email protected]>

* gas/riscv/cv-alu-extbs.d: Fix test after encoding change.
Expand Down
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-march.d
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#as: -march=rv32i
#source: cv-mem-fail-march.s
#error_output: cv-mem-fail-march.l
25 changes: 25 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-march.l
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@@ -0,0 +1,25 @@
.*: Assembler messages:
.*: Error: unrecognized opcode `cv.lb t4,t2\(t0\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lbu t6,t1\(t4\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lh t2,t0\(t3\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lhu t0,t5\(t1\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lw t1,t3\(t6\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lb t4,\(t0\),t2', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),t1', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lh t2,\(t3\),t0', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),t5', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lw t1,\(t6\),t3', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lb t4,\(t0\),23', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lbu t6,\(t4\),0', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lh t2,\(t3\),77', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lhu t0,\(t1\),101', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.lw t1,\(t6\),6', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sb t0,t1\(t2\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sh t1,t3\(t4\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sw t1,t2\(t4\)', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sb t0,\(t2\),t1', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sh t1,\(t2\),t6', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sw t5,\(t2\),t6', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sb t6,\(t1\),10', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sh t3,\(t5\),80', extension `xcvmem' required
.*: Error: unrecognized opcode `cv.sw t1,\(t4\),20', extension `xcvmem' required
26 changes: 26 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-march.s
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@@ -0,0 +1,26 @@
# Absence of xcvmem march option disables all CORE-V mem extensions
target:
cv.lb t4, t2(t0)
cv.lbu t6, t1(t4)
cv.lh t2, t0(t3)
cv.lhu t0, t5(t1)
cv.lw t1, t3(t6)
cv.lb t4, (t0), t2
cv.lbu t6, (t4), t1
cv.lh t2, (t3), t0
cv.lhu t0, (t1), t5
cv.lw t1, (t6), t3
cv.lb t4, (t0), 23
cv.lbu t6, (t4), 0
cv.lh t2, (t3), 77
cv.lhu t0, (t1), 101
cv.lw t1, (t6), 6
cv.sb t0, t1(t2)
cv.sh t1, t3(t4)
cv.sw t1, t2(t4)
cv.sb t0, (t2), t1
cv.sh t1, (t2), t6
cv.sw t5, (t2), t6
cv.sb t6, (t1), 10
cv.sh t3, (t5), 80
cv.sw t1, (t4), 20
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
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@@ -0,0 +1,3 @@
#as: -march=rv32i_xcvmem
#source: cv-mem-fail-operand-01.s
#error_output: cv-mem-fail-operand-01.l
21 changes: 21 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
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@@ -0,0 +1,21 @@
.*: Assembler messages:
.*: Error: illegal operands `cv.lb 20,10\(t1\)'
.*: Error: illegal operands `cv.lb 32,\(t2\),15'
.*: Error: illegal operands `cv.lb 40,t2\(t3\)'
.*: Error: illegal operands `cv.lb 28,\(t4\),t3'
.*: Error: illegal operands `cv.lbu 16,20\(t5\)'
.*: Error: illegal operands `cv.lbu 20,\(t6\),30'
.*: Error: illegal operands `cv.lbu 44,t4\(t1\)'
.*: Error: illegal operands `cv.lbu 48,\(t2\),t5'
.*: Error: illegal operands `cv.lh 52,25\(t3\)'
.*: Error: illegal operands `cv.lh 12,\(t4\),10'
.*: Error: illegal operands `cv.lh 16,t6\(t5\)'
.*: Error: illegal operands `cv.lh 36,\(t6\),t1'
.*: Error: illegal operands `cv.lhu 24,35\(t1\)'
.*: Error: illegal operands `cv.lhu 12,\(t2\),13'
.*: Error: illegal operands `cv.lhu 32,t2\(t3\)'
.*: Error: illegal operands `cv.lhu 40,\(t4\),t3'
.*: Error: illegal operands `cv.lw 44,18\(t5\)'
.*: Error: illegal operands `cv.lw 48,\(t6\),8'
.*: Error: illegal operands `cv.lw 24,t4\(t1\)'
.*: Error: illegal operands `cv.lw 12,\(t2\),t5'
22 changes: 22 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
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@@ -0,0 +1,22 @@
# Destination operand must be a register
target:
cv.lb 20, 10(t1)
cv.lb 32, (t2), 15
cv.lb 40, t2(t3)
cv.lb 28, (t4), t3
cv.lbu 16, 20(t5)
cv.lbu 20, (t6), 30
cv.lbu 44, t4(t1)
cv.lbu 48, (t2), t5
cv.lh 52, 25(t3)
cv.lh 12, (t4), 10
cv.lh 16, t6(t5)
cv.lh 36, (t6), t1
cv.lhu 24, 35(t1)
cv.lhu 12, (t2), 13
cv.lhu 32, t2(t3)
cv.lhu 40, (t4), t3
cv.lw 44, 18(t5)
cv.lw 48, (t6), 8
cv.lw 24, t4(t1)
cv.lw 12, (t2), t5
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
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@@ -0,0 +1,3 @@
#as: -march=rv32i_xcvmem
#source: cv-mem-fail-operand-02.s
#error_output: cv-mem-fail-operand-02.l
13 changes: 13 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
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@@ -0,0 +1,13 @@
.*: Assembler messages:
.*: Error: illegal operands `cv.sb 12,10\(t1\)'
.*: Error: illegal operands `cv.sb 14,\(t2\),20'
.*: Error: illegal operands `cv.sb 16,t1\(t3\)'
.*: Error: illegal operands `cv.sb 20,\(t4\),t2'
.*: Error: illegal operands `cv.sh 30,30\(t5\)'
.*: Error: illegal operands `cv.sh 15,\(t6\),40'
.*: Error: illegal operands `cv.sh 45,t3\(t1\)'
.*: Error: illegal operands `cv.sh 52,\(t2\),t4'
.*: Error: illegal operands `cv.sw 12,12\(t3\)'
.*: Error: illegal operands `cv.sw 10,\(t4\),16'
.*: Error: illegal operands `cv.sw 82,t5\(t5\)'
.*: Error: illegal operands `cv.sw 14,\(t1\),t6'
14 changes: 14 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
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@@ -0,0 +1,14 @@
# Source operand must be a register
target:
cv.sb 12, 10(t1)
cv.sb 14, (t2), 20
cv.sb 16, t1(t3)
cv.sb 20, (t4), t2
cv.sh 30, 30(t5)
cv.sh 15, (t6), 40
cv.sh 45, t3(t1)
cv.sh 52, (t2), t4
cv.sw 12, 12(t3)
cv.sw 10, (t4), 16
cv.sw 82, t5(t5)
cv.sw 14, (t1), t6
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
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#as: -march=rv32i_xcvmem
#source: cv-mem-fail-operand-03.s
#error_output: cv-mem-fail-operand-03.l
33 changes: 33 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
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.*: Assembler messages:
.*: Error: illegal operands `cv.sb t0,10\(12\)'
.*: Error: illegal operands `cv.sb t1,\(24\),20'
.*: Error: illegal operands `cv.sb t2,t1\(25\)'
.*: Error: illegal operands `cv.sb t3,\(75\),t2'
.*: Error: illegal operands `cv.sh t4,30\(13\)'
.*: Error: illegal operands `cv.sh t5,\(16\),40'
.*: Error: illegal operands `cv.sh t6,t3\(31\)'
.*: Error: illegal operands `cv.sh t0,\(37\),t4'
.*: Error: illegal operands `cv.sw t1,12\(51\)'
.*: Error: illegal operands `cv.sw t2,\(43\),16'
.*: Error: illegal operands `cv.sw t3,t5\(61\)'
.*: Error: illegal operands `cv.sw t4,\(67\),t6'
.*: Error: illegal operands `cv.lb t0,12\(12\)'
.*: Error: illegal operands `cv.lb t1,\(24\),13'
.*: Error: illegal operands `cv.lb t2,t3\(25\)'
.*: Error: illegal operands `cv.lb t3,\(75\),t4'
.*: Error: illegal operands `cv.lbu t4,22\(51\)'
.*: Error: illegal operands `cv.lbu t5,\(43\),10'
.*: Error: illegal operands `cv.lbu t6,t5\(61\)'
.*: Error: illegal operands `cv.lbu t0,\(67\),t6'
.*: Error: illegal operands `cv.lh t1,19\(13\)'
.*: Error: illegal operands `cv.lh t2,\(16\),41'
.*: Error: illegal operands `cv.lh t3,t0\(31\)'
.*: Error: illegal operands `cv.lh t4,\(37\),t1'
.*: Error: illegal operands `cv.lhu t5,15\(14\)'
.*: Error: illegal operands `cv.lhu t6,\(17\),12'
.*: Error: illegal operands `cv.lhu t0,t2\(14\)'
.*: Error: illegal operands `cv.lhu t1,\(39\),t3'
.*: Error: illegal operands `cv.lw t2,4\(24\)'
.*: Error: illegal operands `cv.lw t3,\(21\),6'
.*: Error: illegal operands `cv.lw t5,t4\(16\)'
.*: Error: illegal operands `cv.lw t4,\(47\),t5'
34 changes: 34 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
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# Base operand must be a register
target:
cv.sb t0, 10(12)
cv.sb t1, (24), 20
cv.sb t2, t1(25)
cv.sb t3, (75), t2
cv.sh t4, 30(13)
cv.sh t5, (16), 40
cv.sh t6, t3(31)
cv.sh t0, (37), t4
cv.sw t1, 12(51)
cv.sw t2, (43), 16
cv.sw t3, t5(61)
cv.sw t4, (67), t6
cv.lb t0, 12(12)
cv.lb t1, (24), 13
cv.lb t2, t3(25)
cv.lb t3, (75), t4
cv.lbu t4, 22(51)
cv.lbu t5, (43), 10
cv.lbu t6, t5(61)
cv.lbu t0, (67), t6
cv.lh t1, 19(13)
cv.lh t2, (16), 41
cv.lh t3, t0(31)
cv.lh t4, (37), t1
cv.lhu t5, 15(14)
cv.lhu t6, (17), 12
cv.lhu t0, t2(14)
cv.lhu t1, (39), t3
cv.lw t2, 4(24)
cv.lw t3, (21), 6
cv.lw t5, t4(16)
cv.lw t4, (47), t5
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
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#as: -march=rv32i_xcvmem
#source: cv-mem-fail-operand-04.s
#error_output: cv-mem-fail-operand-04.l
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