Added support for CORE-V hardware loop

Added two relocations REL12 and RELU5, the CORE-V INSN_CLASSes, the MATCH and MASKs and the hardware loop instructions. bfd/ChangeLog: * bfd-in2.h: Added CORE-V hardware loop specific relocations. * elfnn-riscv.c: Added relocations for CORE-V hardware loop. * elfxx-riscv.c: Added relocations and amend howto lookup. * riscv.c: Added BFD_RELOC_RISCV_CVPCREL_UI12 and BFD_RELOC_RISCV_CVPCREL_URS1. gas/ChangeLog: * config/tc-riscv.c: Added CORE-V harware loop support. * config/tc-riscv.h: Likewise. * doc/c-riscv.texi: Noted Xcorev as additional ISA extension for CORE-V. gas/testsuite/ChangeLog: * gas/riscv/cv-hwloop-01.d: Added new test. * gas/riscv/cv-hwloop-01.l: Likewise. * gas/riscv/cv-hwloop-01.s: Likewise. * gas/riscv/cv-hwloop-02.d: Likewise. * gas/riscv/cv-hwloop-02.l: Likewise. * gas/riscv/cv-hwloop-02.s: Likewise. * gas/riscv/cv-hwloop-03.d: Likewise. * gas/riscv/cv-hwloop-03.l: Likewise. * gas/riscv/cv-hwloop-03.s: Likewise. * gas/riscv/cv-hwloop-04.d: Likewise. * gas/riscv/cv-hwloop-04.l: Likewise. * gas/riscv/cv-hwloop-04.s: Likewise. * gas/riscv/cv-hwloop-05.d: Likewise. * gas/riscv/cv-hwloop-05.l: Likewise. * gas/riscv/cv-hwloop-05.s: Likewise. * gas/riscv/cv-hwloop-06.d: Likewise. * gas/riscv/cv-hwloop-06.l: Likewise. * gas/riscv/cv-hwloop-06.s: Likewise. * gas/riscv/cv-hwloop-07.d: Likewise. * gas/riscv/cv-hwloop-07.l: Likewise. * gas/riscv/cv-hwloop-07.s: Likewise. * gas/riscv/cv-hwloop-08.d: Likewise. * gas/riscv/cv-hwloop-08.l: Likewise. * gas/riscv/cv-hwloop-08.s: Likewise. * gas/riscv/cv-hwloop-count.d: Likewise. * gas/riscv/cv-hwloop-count.s: Likewise. * gas/riscv/cv-hwloop-counti.d: Likewise. * gas/riscv/cv-hwloop-counti.s: Likewise. * gas/riscv/cv-hwloop-endi.d: Likewise. * gas/riscv/cv-hwloop-endi.s: Likewise. * gas/riscv/cv-hwloop-setup.d: Likewise. * gas/riscv/cv-hwloop-setup.s: Likewise. * gas/riscv/cv-hwloop-setupi.d: Likewise. * gas/riscv/cv-hwloop-setupi.s: Likewise. * gas/riscv/cv-hwloop-starti.d: Likewise. * gas/riscv/cv-hwloop-starti.s: Likewise. * gas/riscv/cv-hwloop-09.d: Likewise. * gas/riscv/cv-hwloop-09.l: Likewise. * gas/riscv/cv-hwloop-09.s: Likewise. * gas/riscv/cv-hwloop-10.d: Likewise. * gas/riscv/cv-hwloop-10.l: Likewise. * gas/riscv/cv-hwloop-10.s: Likewise. include/ChangeLog: * elf/riscv.h: Added CORE-V hardware loop specific relocations. * opcode/riscv.h: Added CORE-V hardware loop specific masks and CORE-V instruction class. Added macros for unsigned I type immediate and loop number. ld/ChangeLog: * emultempl/riscvelf.em: Added initial CORE-V support. ld/testsuite/ChangeLog: * ld-riscv-elf/ld-riscv-elf.exp: Added CORE-V hardware loop tests. * ld-riscv-elf/cv-hwloop-starti.s: Added new test. * ld-riscv-elf/cv-hwloop-starti.d: Likewise. * ld-riscv-elf/cv-hwloop-endi.d: Likewise. * ld-riscv-elf/cv-hwloop-endi.s: Likewise. * ld-riscv-elf/cv-hwloop-setup.d: Likewise. * ld-riscv-elf/cv-hwloop-setup.s: Likewise. * ld-riscv-elf/cv-hwloop-setupi.d: Likewise. * ld-riscv-elf/cv-hwloop-setupi.s: Likewise. opcodes/ChangeLog: * riscv-dis.c: Added CORE-V hardware loop support. * riscv-opc.c: Likewise. Signed-off-by: Mary Bennett <[email protected]> Added new boundary tests & fixed boundary check bug in hwloop & mac Signed-off-by: Jessica Mills <[email protected]> RISC-V: Fixed the overflow values for cv relocations Issue #73: #73 The issue describes a problem with the hardware loop relocations; they do not properly check for overflow. The function bfd_check_overflow in bfd/reloc.c was used to check for overflow by the assembler. It has now been moved to the linker. Files Changed: * bfd/elfnn-riscv.c (perform_relocation): Added overflow check for R_RELOC_RISCV_CVPCREL_UI12 and R_RELOC_RISCV_CVPCREL_URS1. * gas/config/tc-riscv.c(md_apply_fix): Removed the assembler relocation overflow check for R_RELOC_RISCV_CVPCREL_UI12 and R_RELOC_RISCV_CVPCREL_URS1. ld/testsuite/ld-riscv-elf: * cv-hwlp-pass.d: New test. * cv-hwlp-pass.s: Likewise. * cv-hwlp-setupi-2.d: Likewise. * cv-hwlp-setupi-2.s: Likewise. * cv-hwlp-setupi-fail.d: Likewise. * cv-hwlp-setupi-fail.l: Likewise. * cv-hwlp-setupi-fail.s: Likewise. * cv-hwlp-starti-2.d: Likewise. * cv-hwlp-starti-2.s: Likewise. * cv-hwlp-starti-fail.d: Likewise. * cv-hwlp-starti-fail.l: Likewise. * cv-hwlp-starti-fail.s: Likewise. * ld-riscv-elf.exp: Likewise.
openhwgroup · Oct 2, 2023 · f9a073f · f9a073f
1 parent da67d04
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diff --git a/bfd/ChangeLog.COREV b/bfd/ChangeLog.COREV
@@ -0,0 +1,17 @@
+2020-11-10  Mary Bennett  <[email protected]>
+
+	* elfnn-riscv.c (perform_relocation): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+	ENCODE_I1TYPE_LN   -> ENCODE_CV_HWLP_LN
+	* elfxx-riscv.c: Renamed macros for clarity -
+	EXTRACT_I1TYPE_UIMM-> EXTRACT_CV_HWLP_UIMM5
+	EXTRACT_I1TYPE_LN  -> EXTRACT_CV_HWLP_LN
+	EXTRACT_ITYPE_UIMM -> EXTRACT_CV_HWLP_UIMM12
+
+2020-09-10  Pietra Ferreira  <[email protected]>
+
+	* bfd-in2.h: Added CORE-V hardware loop specific relocations.
+	* elfnn-riscv.c: Added relocations for CORE-V hardware loop.
+	* elfxx-riscv.c: Added relocations and amend howto lookup.
+	* bfd/riscv.c: Added BFD_RELOC_RISCV_CVPCREL_UI12 and
+	BFD_RELOC_RISCV_CVPCREL_URS1.
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
@@ -5441,6 +5441,10 @@ number for the SBIC, SBIS, SBI and CBI instructions  */
   BFD_RELOC_RISCV_SET_ULEB128,
   BFD_RELOC_RISCV_SUB_ULEB128,
 
+/* CORE-V relocations.  */
+  BFD_RELOC_RISCV_CVPCREL_UI12,
+  BFD_RELOC_RISCV_CVPCREL_URS1,
+
 /* Renesas RL78 Relocations.  */
   BFD_RELOC_RL78_NEG8,
   BFD_RELOC_RL78_NEG16,

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
@@ -4,6 +4,13 @@
    Contributed by Andrew Waterman ([email protected]).
    Based on TILE-Gx and MIPS targets.
 
+   Modified for CORE-V by:
+   Mary Bennett ([email protected])
+   Pietra Ferreira ([email protected])
+   Jessica Mills ([email protected])
+
+   Some of these changes are (C) Open Hardware Group, pending FSF assignment.
+
    This file is part of BFD, the Binary File Descriptor library.
 
    This program is free software; you can redistribute it and/or modify
@@ -1752,6 +1759,27 @@ perform_relocation (const reloc_howto_type *howto,
       value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
       break;
 
+    /* CORE-V Specific Relocations.  */
+    case R_RISCV_CVPCREL_UI12:
+      if (bfd_check_overflow (howto->complain_on_overflow, 12, 0,
+	    bfd_get_reloc_size (howto) * 8, value >> howto->rightshift)
+		     != bfd_reloc_overflow)
+      {
+        value = ENCODE_ITYPE_IMM (value >> howto->rightshift);
+        break;
+      }
+      return bfd_reloc_overflow;
+
+    case R_RISCV_CVPCREL_URS1:
+      if (bfd_check_overflow (howto->complain_on_overflow, 5, 0,
+	    bfd_get_reloc_size (howto) * 8, value >> howto->rightshift)
+		     != bfd_reloc_overflow)
+      {
+	value = ENCODE_CV_HWLP_UIMM5 (value >> howto->rightshift);
+	break;
+      }
+      return bfd_reloc_overflow;
+
     case R_RISCV_LO12_I:
     case R_RISCV_GPREL_I:
     case R_RISCV_TPREL_LO12_I:
@@ -2500,6 +2528,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	case R_RISCV_SET32:
 	case R_RISCV_32_PCREL:
 	case R_RISCV_DELETE:
+	/* CORE-V Specific.  */
+	case R_RISCV_CVPCREL_URS1:
+	case R_RISCV_CVPCREL_UI12:
 	  /* These require no special handling beyond perform_relocation.  */
 	  break;
 

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
@@ -879,6 +879,37 @@ static reloc_howto_type howto_table[] =
 	 0,				/* src_mask */
 	 0,				/* dst_mask */
 	 false),			/* pcrel_offset */
+
+  /* CORE-V Specific.  */
+  /* 12-bit PC-relative offset, for hwloop.  */
+  HOWTO (R_RISCV_CVPCREL_UI12,		/* type */
+	 2,				/* rightshift */
+	 2,				/* size */
+	 32,				/* bitsize */
+	 true,				/* pc_relative */
+	 0,				/* bitpos */
+	 complain_overflow_unsigned,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,		/* special_function */
+	 "R_RISCV_CVPCREL_UI12",	/* name */
+	 false,				/* partial_inplace */
+	 0,				/* src_mask */
+	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
+	 true),				/* pcrel_offset */
+
+  /* Unsigned 5-bit PC-relative offset, for hwloop.  */
+  HOWTO (R_RISCV_CVPCREL_URS1,		/* type */
+	 2,				/* rightshift */
+	 1,				/* size */
+	 32,				/* bitsize */
+	 true,				/* pc_relative */
+	 0,				/* bitpos */
+	 complain_overflow_unsigned,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,		/* special_function */
+	 "R_RISCV_CVPCREL_URS1",	/* name */
+	 false,				/* partial_inplace */
+	 0,				/* src_mask */
+	 ENCODE_CV_HWLP_UIMM5 (-1U),	/* dst_mask */
+	 true),				/* pcrel_offset */
 };
 
 /* A mapping from BFD reloc types to RISC-V ELF reloc types.  */
@@ -942,47 +973,53 @@ static const struct elf_reloc_map riscv_reloc_map[] =
   { BFD_RELOC_RISCV_32_PCREL, R_RISCV_32_PCREL },
   { BFD_RELOC_RISCV_SET_ULEB128, R_RISCV_SET_ULEB128 },
   { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
+  /* CORE-V Specific.  */
+  { BFD_RELOC_RISCV_CVPCREL_UI12, R_RISCV_CVPCREL_UI12 },
+  { BFD_RELOC_RISCV_CVPCREL_URS1, R_RISCV_CVPCREL_URS1 },
 };
 
-/* Given a BFD reloc type, return a howto structure.  */
-
 reloc_howto_type *
-riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-			 bfd_reloc_code_real_type code)
+riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
 {
   unsigned int i;
 
-  for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++)
-    if (riscv_reloc_map[i].bfd_val == code)
-      return &howto_table[(int) riscv_reloc_map[i].elf_val];
+  for (i = 0; i < ARRAY_SIZE (howto_table); i++)
+    if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0)
+      return &howto_table[i];
 
-  bfd_set_error (bfd_error_bad_value);
   return NULL;
 }
 
 reloc_howto_type *
-riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+riscv_elf_rtype_to_howto (bfd *abfd, unsigned int r_type)
 {
   unsigned int i;
-
   for (i = 0; i < ARRAY_SIZE (howto_table); i++)
-    if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0)
-      return &howto_table[i];
+    {
+      if (r_type == howto_table[i].type)
+	return &howto_table[i];
+    }
 
+  (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"),
+			 abfd, r_type);
+  bfd_set_error (bfd_error_bad_value);
   return NULL;
 }
 
+/* Given a BFD reloc type, return a howto structure.  */
+
 reloc_howto_type *
-riscv_elf_rtype_to_howto (bfd *abfd, unsigned int r_type)
+riscv_reloc_type_lookup (bfd *abfd,
+			 bfd_reloc_code_real_type code)
 {
-  if (r_type >= ARRAY_SIZE (howto_table))
-    {
-      (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"),
-			     abfd, r_type);
-      bfd_set_error (bfd_error_bad_value);
-      return NULL;
-    }
-  return &howto_table[r_type];
+  unsigned int i;
+
+  for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++)
+    if (riscv_reloc_map[i].bfd_val == code)
+      return riscv_elf_rtype_to_howto(abfd, riscv_reloc_map[i].elf_val);
+
+  bfd_set_error (bfd_error_bad_value);
+  return NULL;
 }
 
 /* Special_function of RISCV_ADD and RISCV_SUB relocations.  */
@@ -1354,6 +1391,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvhwlp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2556,6 +2594,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XCVHWLP:
+      return riscv_subset_supports (rps, "xcvhwlp");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2800,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmac";
     case INSN_CLASS_XCVALU:
       return "xcvalu";
+    case INSN_CLASS_XCVHWLP:
+      return "xcvhwlp";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:

diff --git a/bfd/libbfd.h b/bfd/libbfd.h
@@ -2422,6 +2422,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_RISCV_32_PCREL",
   "BFD_RELOC_RISCV_SET_ULEB128",
   "BFD_RELOC_RISCV_SUB_ULEB128",
+  "BFD_RELOC_RISCV_CVPCREL_UI12",
+  "BFD_RELOC_RISCV_CVPCREL_URS1",
   "BFD_RELOC_RL78_NEG8",
   "BFD_RELOC_RL78_NEG16",
   "BFD_RELOC_RL78_NEG24",

diff --git a/bfd/reloc.c b/bfd/reloc.c
@@ -5055,6 +5055,13 @@ ENUMX
 ENUMDOC
   RISC-V relocations.
 
+ENUM
+  BFD_RELOC_RISCV_CVPCREL_UI12
+ENUMX
+  BFD_RELOC_RISCV_CVPCREL_URS1
+ENUMDOC
+  CORE-V relocations.
+
 ENUM
   BFD_RELOC_RL78_NEG8
 ENUMX

diff --git a/gas/ChangeLog.COREV b/gas/ChangeLog.COREV
@@ -0,0 +1,36 @@
+2021-08-23  Jessica Mills  <[email protected]>
+
+	* config/tc-riscv.c (riscv_ip): Fix boundary bug for hardware loop
+	branch operands - upper boundary of long branch offset changed from
+	4094 to 8191 and short offset from 30 to 63.
+
+2020-11-24  Jessica Mills  <[email protected]>
+
+	* doc/c-riscv.texi: Added details on CORE-V hardware loop,
+	multiply-accumulate and general ALU ops ISA options.
+
+2020-11-19  Jessica Mills  <[email protected]>
+
+	* config/tc-riscv.c: Fixed bug in hardware loop operand boundary
+	checks (b1 and b2).
+
+2020-11-10  Mary Bennett  <[email protected]>
+
+	* config/tc-riscv.c (validate_riscv_insn): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+	ENCODE_I1TYPE_LN   -> ENCODE_CV_HWLP_LN
+	* config/tc-riscv.c (md_apply_fix): Renamed macros for clarity -
+	ENCODE_I1TYPE_UIMM -> ENCODE_CV_HWLP_UIMM5
+
+2020-10-05  Mary Bennett <[email protected]>
+
+	* config/tc-riscv.c: Fixed issue arising from incorrect CORE-V
+	hardware loop masks and added support for xcorevhwlp and new
+	error messages.
+
+2020-09-10  Pietra Ferreira  <[email protected]>
+
+	* config/tc-riscv.c: Added CORE-V hardware loop support.
+	* config/tc-riscv.h: Likewise.
+	* doc/c-riscv.texi: Noted Xcorev as additional ISA extension
+	 for CORE-V.