Add branching immediate instructions, and GAS tests

Signed-off-by: Nazareno Bruschi <[email protected]>

Remove hardcoded address in xcvbi testcases

Author: @linsinan1995

Immediate Branching Version 2 Instructions and Tests Encodings Updated

	include/opcode:
	    * riscv-opc.h: Added corresponding MATCH and MASK
	      macros for Immediate Branching.

	gas/testsuite/gas/riscv:
	    * gas/testsuite/gas/riscv/cv-bi-beqimm.d
	    * gas/testsuite/gas/riscv/cv-bi-bneimm.d
	    * gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.d

Signed-off-by: Nandni Jamnadas <[email protected]>

tests

bfd/elfxx-riscv.c

@@ -1393,6 +1393,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvhwlp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvmem",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvbi",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2599,6 +2600,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvhwlp");
     case INSN_CLASS_XCVMEM:
       return riscv_subset_supports (rps, "xcvmem");
+    case INSN_CLASS_XCVBI:
+      return riscv_subset_supports (rps, "xcvbi");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2847,6 +2850,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvhwlp";
     case INSN_CLASS_XCVMEM:
       return "xcvmem";
+    case INSN_CLASS_XCVBI:
+      return "xcvbi";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:

gas/ChangeLog.COREV

@@ -1,3 +1,14 @@
+2021-08-10  Nazareno Bruschi  <[email protected]>
+
+	* config/tc-riscv.c (riscv_multi_subset_supports): Add immediate
+	branching instruction class.
+	(validate_riscv_insn, riscv_ip): Rename macro
+	ENCODE_CV_ALU_UIMM5 -> ENCODE_CV_UIMM5.
+	(validate_riscv_insn, riscv_ip): Add immediate branching
+	operand and modify PC-relative offset operand.
+	* doc/c-riscv.texi: Add details on CORE-V immediate
+	branching ops ISA options.
+
 2021-08-06  Enrico Tabanelli  <[email protected]>
 
 	* config/tc-riscv.c (riscv_multi_subset_supports): Add 

gas/config/tc-riscv.c

@@ -1385,6 +1385,11 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      used_bits |= ENCODE_CV_HWLP_UIMM5(-1U);
 	      ++oparg; break;
 	    }
+	  else if (oparg[1] == '4')
+	    {
+	      used_bits |= ENCODE_CV_UIMM5(-1U);
+	      ++oparg; break;
+	    }
 	  break;
 	case 'c': break; /* Macro operand, must be symbol or constant.  */
 	case 'I': break; /* Macro operand, must be constant.  */
@@ -3337,9 +3342,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      asarg = expr_parse_end;
 	      continue;
 	      /* CORE-V Specific.
-	         b1: pc rel 12 bits offset for cv.starti and cv.endi
-	             sign-extended immediate as pc rel displacement for hwloop
-	         b2: pc rel 5 bits unsigned offset for cv.setupi  */
+		 b1: pc rel 12 bits offset for cv.starti and cv.endi
+		     sign-extended immediate as pc rel displacement for hwloop
+		 b2: pc rel 5 bits unsigned offset for cv.setupi
+		 b3: 5 bits usigned offset for MAC
+		 b4: 5 bits signed immediate bits[24..20]
+		 bi: 5 bits unsigned offset for cv.clip and cv.clipu
+		     ALU luimm5 [24...20]	 */
 	    case 'b':
 	      if (oparg[1] == '1')
 		{
@@ -3404,6 +3413,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		    *imm_reloc = BFD_RELOC_RISCV_CVPCREL_URS1;
 		  }
 		}
+	      else if (oparg[1] == '4')
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-16 || imm_expr->X_add_number>15)
+		  as_bad(_("immediate value must be 5-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_UIMM5 (imm_expr->X_add_number);
+		  ++oparg;
+		}
 	      else
 		{
 		  my_getExpression (imm_expr, asarg);

gas/doc/c-riscv.texi

@@ -765,6 +765,11 @@ The Xcvmem extension provides instructions for post inc load/store operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvbi
+The Xcvbi extension provides instructions for branch immediate operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 

gas/testsuite/ChangeLog.COREV

@@ -1,3 +1,27 @@
+2021-08-10  Nazareno Bruschi  <[email protected]>
+
+	* gas/riscv/cv-bi-beqimm.d: Add immediate branching test.
+	* gas/riscv/cv-bi-beqimm.s: Likewise.
+	* gas/riscv/cv-bi-bneimm.d: Likewise.
+	* gas/riscv/cv-bi-bneimm.s: Likewise.
+	* gas/riscv/cv-bi-fail-march.d: Likewise.
+	* gas/riscv/cv-bi-fail-march.l: Likewise.
+	* gas/riscv/cv-bi-fail-march.s: Likewise.
+	* gas/riscv/cv-bi-fail-operand-01.d: Likewise.
+	* gas/riscv/cv-bi-fail-operand-01.l: Likewise.
+	* gas/riscv/cv-bi-fail-operand-01.s: Likewise.
+	* gas/riscv/cv-bi-fail-operand-02.d: Likewise.
+	* gas/riscv/cv-bi-fail-operand-02.l: Likewise.
+	* gas/riscv/cv-bi-fail-operand-02.s: Likewise.
+	* gas/riscv/cv-bi-fail-operand-03.d: Likewise.
+	* gas/riscv/cv-bi-fail-operand-03.l: Likewise.
+	* gas/riscv/cv-bi-fail-operand-03.s: Likewise.
+	* gas/riscv/cv-bi-fail-operand-04.d: Likewise.
+	* gas/riscv/cv-bi-fail-operand-04.l: Likewise.
+	* gas/riscv/cv-bi-fail-operand-04.s: Likewise.
+	* gas/riscv/cv-bi-march-rv32i-xcorev.d: Likewise.
+	* gas/riscv/cv-bi-march-rv32i-xcorev.s: Likewise.
+
 2021-08-06  Enrico Tabanelli  <[email protected]>
 
 	* gas/riscv/cv-mem-fail-operand-01.d: Add post-increment

gas/testsuite/gas/riscv/cv-bi-beqimm.d

@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+0102e00b[ 	]+cv.beqimm[ 	]+t0,-16,0 +<foo>
+[ 	]+4:[ 	]+fe5eee8b[ 	]+cv.beqimm[ 	]+t4,5,0 +<foo>
+[ 	]+8:[ 	]+fef3ec8b[ 	]+cv.beqimm[ 	]+t2,15,0 +<foo>

gas/testsuite/gas/riscv/cv-bi-beqimm.s

@@ -0,0 +1,4 @@
+foo:
+	cv.beqimm t0, -16, foo
+	cv.beqimm t4, 5, foo
+	cv.beqimm t2, 15, foo

gas/testsuite/gas/riscv/cv-bi-bneimm.d

@@ -0,0 +1,12 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+0102f00b[ 	]+cv.bneimm[ 	]+t0,-16,0 +<foo>
+[ 	]+4:[ 	]+fe5efe8b[ 	]+cv.bneimm[ 	]+t4,5,0 +<foo>
+[ 	]+8:[ 	]+fef3fc8b[ 	]+cv.bneimm[ 	]+t2,15,0 +<foo>

gas/testsuite/gas/riscv/cv-bi-bneimm.s

@@ -0,0 +1,4 @@
+foo:
+	cv.bneimm t0, -16, foo
+	cv.bneimm t4, 5, foo
+	cv.bneimm t2, 15, foo

gas/testsuite/gas/riscv/cv-bi-fail-march.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-bi-fail-march.s
+#error_output: cv-bi-fail-march.l

gas/testsuite/gas/riscv/cv-bi-fail-march.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required
+.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required

gas/testsuite/gas/riscv/cv-bi-fail-march.s

@@ -0,0 +1,5 @@
+# Absence of xcorev or xcorevbi march option disables all CORE-V
+# immediate branching extensions.
+foo:
+	cv.beqimm t2, 1, foo
+	cv.bneimm t2, 1, foo

gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-01.s
+#error_output: cv-bi-fail-operand-01.l

gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.beqimm 20,10,foo'
+.*: Error: illegal operands `cv.bneimm 8,-4,foo'

gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s

@@ -0,0 +1,4 @@
+# Comparison target must be a register
+foo:
+	cv.beqimm 20, 10, foo
+	cv.bneimm 8, -4, foo

gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-02.s
+#error_output: cv-bi-fail-operand-02.l

gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: instruction cv.beqimm requires absolute expression
+.*: Error: instruction cv.bneimm requires absolute expression

gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s

@@ -0,0 +1,4 @@
+# Comparison value must be an immediate
+foo:
+	cv.beqimm t0, t1, foo
+	cv.bneimm t3, t4, foo

gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbi
+#source: cv-bi-fail-operand-03.s
+#error_output: cv-bi-fail-operand-03.l

gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l

@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: immediate value must be 5-bit signed, -17 is out of range
+.*: Error: immediate value must be 5-bit signed, -32 is out of range
+.*: Error: immediate value must be 5-bit signed, 16 is out of range
+.*: Error: immediate value must be 5-bit signed, 44 is out of range
+.*: Error: immediate value must be 5-bit signed, -17 is out of range
+.*: Error: immediate value must be 5-bit signed, -32 is out of range
+.*: Error: immediate value must be 5-bit signed, 16 is out of range
+.*: Error: immediate value must be 5-bit signed, 44 is out of range

gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s

@@ -0,0 +1,10 @@
+# Comparison value must be an immediate in range [-16, +15]
+foo:
+	cv.beqimm t0, -17, foo
+	cv.beqimm t2, -32, foo
+	cv.beqimm t4, 16, foo
+	cv.beqimm t3, 44, foo
+	cv.bneimm t0, -17, foo
+	cv.bneimm t2, -32, foo
+	cv.bneimm t4, 16, foo
+	cv.bneimm t3, 44, foo

gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.d

@@ -0,0 +1,11 @@
+#as: -march=rv32i_xcvbi
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+0:[ 	]+0013e00b[ 	]+cv.beqimm[ 	]+t2,1,0 +<foo>
+[ 	]+4:[ 	]+ff02fe8b[ 	]+cv.bneimm[ 	]+t0,-16,0 +<foo>

gas/testsuite/gas/riscv/cv-bi-march-rv32i-xcorev.s

@@ -0,0 +1,4 @@
+# xcorev march option works for all CORE-V immediate branching extensions
+foo:
+	cv.beqimm t2, 1, foo
+	cv.bneimm t0, -16, foo

include/ChangeLog.COREV

@@ -1,3 +1,13 @@
+2021-08-10  Nazareno Bruschi  <[email protected]>
+
+	* opcode/riscv-opc.h: Add immediate branching matches and
+	masks.
+	* opcode/riscv.h (riscv_insn_class, EXTRACT_CV_BI_IMM5):
+	Add immediate branching class and macros for 5-bit signed
+	immediate.
+	(ENCODE_CV_ALU_UIMM5): Rename macro as ENCODE_CV_UIMM5.
+	(RV_IMM_SIGN_N): Add macro for general sign extraction.
+
 2021-08-06  Enrico Tabanelli  <[email protected]>
 
 	* riscv-opc.h: Add post-increment and register-indexed 

include/opcode/riscv-opc.h

@@ -2479,6 +2479,11 @@
 #define MASK_CV_SPOST     0x707f
 #define MASK_CV_SRRPOST   0xfe00707f
 #define MASK_CV_SRR       0xfe00707f
+/* Vendor-specific (CORE-V) Xcvbi instructions. */
+#define MATCH_CV_BNEIMM    0x700b
+#define MATCH_CV_BEQIMM    0x600b
+#define MASK_CV_BNEIMM     0x707f
+#define MASK_CV_BEQIMM     0x707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f

include/opcode/riscv.h

@@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
+#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
 
 #define EXTRACT_ITYPE_IMM(x) \
   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
@@ -123,6 +124,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 7, 1))
 #define EXTRACT_CV_HWLP_UIMM12(x) \
   (RV_X(x, 20, 12))
+#define EXTRACT_CV_BI_IMM5(x) \
+  (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -183,6 +186,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 5) << 15)
 #define ENCODE_CV_HWLP_LN(x) \
   (RV_X(x, 0, 1) << 7)
+#define ENCODE_CV_UIMM5(x) \
+  (RV_X(x, 0, 5) << 20)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -475,6 +480,7 @@ enum riscv_insn_class
   INSN_CLASS_XCVALU,
   INSN_CLASS_XCVHWLP,
   INSN_CLASS_XCVMEM,
+  INSN_CLASS_XCVBI,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,

ld/testsuite/ChangeLog.COREV

@@ -1,3 +1,21 @@
+2021-08-23  Lin Sinan  <[email protected]>
+
+	* ld-riscv-elf/cv-bi-beqimm.d: Remove hard coded address.
+	* ld-riscv-elf/cv-bi-bneimm.d: Likewise.
+	* ld-riscv-elf/cv-hwlp-starti.d: Likewise.
+	* ld-riscv-elf/cv-hwlp-endi.d: Likewise.
+	* ld-riscv-elf/cv-hwlp-setupi.d: Likewise.
+	* ld-riscv-elf/cv-hwlp-setup.d: Likewise.
+
+2021-08-10  Nazareno Bruschi  <[email protected]>
+
+	* ld-riscv-elf/cv-bi-beqimm.d: Add new test.
+	* ld-riscv-elf/cv-bi-beqimm.s: Likewise.
+	* ld-riscv-elf/cv-bi-bneimm.d: Likewise.
+	* ld-riscv-elf/cv-bi-bneimm.s: Likewise.
+	* ld-riscv-elf/ld-riscv-elf.exp: Add CORE-V immediate
+	branching tests.
+
 2021-08-23  Jessica Mills  <[email protected]>
 
 	* ld-riscv-elf/ld-riscv-elf.exp: Renamed CORE-V hwlp tests to match

ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d

@@ -0,0 +1,21 @@
+#name: beqimm relocation
+#source: cv-bi-beqimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass

ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s

@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.beqimm       t0, -16, L2
+        call func
+L2:     nop

ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d

@@ -0,0 +1,21 @@
+#name: bneimm relocation
+#source: cv-bi-bneimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass

ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s

@@ -0,0 +1,11 @@
+        .option nopic
+        .text
+        .align 1
+        .globl _start
+        .type _start, @function
+
+func:   ret
+_start:
+        cv.bneimm       t0, -16, L2
+        call func
+L2:     nop