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Tricky‐to‐Emulate Games
This is a list of games that I observed as being tricky to emulate for one reason or another, which I hope will be helpful to anyone else who wants to write an emulator for one of these consoles.
Most of these are due to games depending on features or hardware quirks that few other games depend on. Some of these are due to requiring a higher level of timing accuracy than many other games.
This list is by no means comprehensive; it's simply a list of games that gave me trouble or that I noticed giving someone else trouble.
See also this link for some more details on some of the Genesis games: https://gendev.spritesmind.net/forum/viewtopic.php?f=2&t=1308
Status bar rendering depends on an SMS1 VDP hardware bug related to certain bits in VDP register #2 masking out part of the nametable address
Uses the VDP's infrequently-used 224-line mode
Uses the TMS9918 Graphics II mode
Plays PCM samples through the PSG's tone channels by rapidly adjusting their volumes
Uses VRAM-to-VRAM copy DMA
Depends on correct emulation of VRAM fill DMA quirks
Stage select graphics depend on correctly emulating X=0 sprite masking quirks
Factor 5 logo is sensitive to VINT timing
Special stages are sensitive to HINT timing and the HV counter
Depends on stalling the 68000 during memory-to-VRAM DMA or there will be glitched graphics in the bottom part of the screen
Depends on correct HINT counter implementation or there will be a glitchy line near the bottom of the title screen
3D chase stages depend on the VDP fetching fewer sprite tiles for the next line if forced blanking is enabled during part of HBlank
This is difficult to emulate accurately, so some emulators (including mine in a previous version) fake this by checking for a certain number of X=0 sprites at the start of the sprite attribute table after filtering to which sprites are on the current line. This doesn't work for certain demos (e.g. Titan Overdrive's 512-color screen) but it fixes Mickey Mania
Screen tearing if VDP FIFO timing is not emulated
Spinning planet animation in the intro depends on VDP FIFO timing
Title screen graphics depend on VDP FIFO timing
Depends on the 256/320 sprite pixel per scanline limit to hide the bottom half of Sonic on the title screen
Uses double-screen interlaced mode (320x448i)
Title screen animation depends on the HV counter latch bit
Sensitive to HINT timing and the HV counter
Requires correct emulation of the HINT pending flag when HINTs are disabled
Intro text scroll is sensitive to HINT timing
Reflection effect in Stage 2 depends on the sprite attribute table cache
Graphical effects during the Two-Face fight depend on writes to VDP nametable address registers taking effect immediately (these registers are not latched)
Some music is prone to have buzzing/popping noises if audio resampling is inaccurate, e.g. song number 1 in music test
EA logo animation depends on officially undocumented VDP port behaviors
Depends on correctly handling 68000 interrupt priority and acknowledging when both HINT and VINT are pending
Depends on the 68000 TAS instruction never writing to memory because it can't lock the bus
Trivia: This game does not work on the Model 3 Genesis actual hardware because that model does allow TAS to lock the bus and write to memory, which breaks this game
Depends on ignoring writes to higher-numbered VDP registers while the VDP is in mode 4 (SMS mode)
Depends on emulating VDP FIFO timing and memory refresh delay or main menu graphics will be corrupted
Depends on emulating memory refresh delay or there will be a glitched line in the intro animation
Uses an EEPROM flash memory chip for save data instead of battery-backed SRAM
Requires fairly accurate VDP DMA timing or graphics will be corrupted
Depends on emulating the mapper register at $A130F1 (controls whether ROM or SRAM is mapped to the SRAM address range)
Only officially licensed game that uses a bank-switching mapper
Some graphics depend on the VDP ignoring sprite Y bit 9 outside of double-screen interlaced mode
Some music sounds wrong if YM2612 DAC crossover distortion is not emulated (aka the "ladder effect")
Music depends on initializing all YM2612 L/R panning flags to 1
Some music depends on skipping attack phase if an operator is keyed on while attenuation is already at 0 (e.g. "3-Prayer" in sound test)
Music tempo is heavily affected by whether games can read the YM2612 busy flag from $4000-$4003 or only $4000
This is technically a difference in behavior between early Model 1 consoles (busy only at $4000) and later consoles (busy at $4000-$4003)
Has bizarre code for reading controller inputs; will not read button presses correctly if not handled properly
Depends on the Z80 BUSACK bit in $A11100 changing almost immediately in response to writes to the Z80 BUSREQ bit ($A11100) or the Z80 RESET bit ($A11200)
Depends on unused bits in the Z80 BUSACK register ($A11100) not all reading 0; in actual hardware they're open bus
Depends on the 68000 getting to execute one more instruction before handling VINT if it re-enables VINTs while a VINT is pending
Somewhat sensitive to the sprite overflow flag in the VDP status register
Has an unusual ROM address mapping where it expects the third MB of its 3MB ROM to be mapped to $300000-$3FFFFF ($200000-$20FFFF should be SRAM)
Depends on the 68000 being able to read the VINT flag in the VDP status register as 1 slightly before the 68000 handles the interrupt
Audio driver depends on undocumented Z80 behavior regarding how the BIT instruction sets the S and P/V flags
Depends on the VDP control port write flag (first/second) getting reset if a game writes to the VDP data port while it is in read mode; otherwise the intro graphics may be randomly corrupted
Depends on the 68000 not being allowed to write to Z80 audio RAM unless the Z80 is removed from the bus and not reset; otherwise it will freeze during the title screen animation
Leaves the Z80 in interrupt mode 0 instead of switching it to interrupt mode 1; should still execute rst $38 when handling interrupts because the Z80 will always read opcode 0xFF from the bus during mode 0 interrupt handling
Requires emulating the SVP coprocessor (Sega Virtua Processor)
Depends on acknowledging INT5 when handled by the sub CPU even if the interrupt handler doesn't acknowledge the interrupt in the CDC's STAT3/DTACK registers
Does VDP DMAs that read all the way to the end of word RAM ($240000); some background graphics will be corrupted if not handled correctly
Puts the sprite attribute table at the highest possible address in VRAM ($FE00 in H32 mode)
Depends on the sub CPU's TAS instruction being able to write to memory, unlike the main CPU's TAS instruction
Depends on correctly setting the 68000's zero flag after DIVU/DIVS instructions (should be set based only on the 16-bit quotient, not the full 32-bit value written to the register)
Depends on correctly handling sub CPU INT1 masking
Intro animation depends on semi-accurate graphics ASIC timing or it will run too fast
Depends on correctly handling byte-size writes to the communication flags registers (writing to either flags register address should modify the writing CPU's 8-bit flags value)
Depends on not allowing the main CPU or the Z80 to write to PRG RAM unless the sub CPU is removed from the bus; otherwise it will freeze after the title screen
Sound effects depend on PCM current address registers returning the channel's start address if the channel is not playing
Depends on CDD status byte 1 reading 0x0F (not ready) while the drive is seeking, track skipping, or stopped
Map graphics depend on halting the sub CPU if it accesses word RAM while it's in 2M mode and owned by the main CPU
Depends on the CDD continuing to read at least one more sector if it receives a command while the drive is playing
Extremely sensitive to there being a long enough delay between the game sending a CDD Read/Play command and the drive reading the first sector
Extremely sensitive to timing accuracy between the two 68000s due to sloppy code around word RAM handoffs; will randomly freeze during gameplay if not handled correctly
Requires RAM cartridge emulation to be able to completely finish the game; the 8KB backup RAM isn't large enough to fit save files for both stories
FMV cutscenes depend on resetting CDC DMA state on all writes to the CDC device destination register
Depends on correctly handling word RAM bank interleaving in 1M mode
Depends on VRAM fill DMA timing to avoid triggering a data race between the two 68000s that causes a freeze
Depends on PRG RAM write protection not applying to writes from the main CPU
Depends on correct handling of 68000 divide by zero exceptions
Depends on the SH7604 user break address registers being R/W; the slave SH-2 abuses them to store audio processing state
Requires semi-accurate emulation of SH-2 CPU cache and SH-2 memory access timing or it will run way too fast
Does some truly strange things with the PWM chip when playing some sound effects, including using different sample rates for different sound effects
Requires close synchronization of the two SH-2s whenever they access the 32X communication ports; otherwise background scrolling won't work and eventually the game will freeze
What happens is that the slave SH-2 sometimes writes to one of the communication ports twice in quick succession, and if the master SH-2 doesn't see the first write then the game will break
Depends on the 32X VDP's FEN bit briefly reading 1 at the start of every line (during DRAM refresh); otherwise it will freeze after the splash screen
If SH-2 CPU cache is emulated, depends on SH7604 DMA reads ignoring CPU cache
Depends on 32X VDP auto fill timing and the FEN bit reading 1 during auto fills, or else there will be a glitched frame every time user inputs change
Uses an EEPROM chip for save data instead of battery-backed SRAM
Sets the Genesis VDP to H32 mode in menus and expects the 320x224 32X VDP output to overlay the 256x224 Genesis VDP output, with 5 H320px pixels for every 4 H256px pixels
Depends on the frame buffer being mirrored at $04040000-$0405FFFF in the SH-2 memory map
Depends on frame buffer swaps taking effect immediately while the 32X VDP is in blank mode, even during active display
Depends on what seem to be undocumented SH7604 DIVU register mirrors; it expects $FFFFFF18 to mirror $FFFFFF10 (DVDNTH), and $FFFFFF1C to mirror $FFFFFF14 (DVDNT / DVDNTL)
Depends on the DREQ FIFO discarding any writes from the 68000 that occur after the DREQ length decrements to 0
Requires emulation of SH-2 CPU cache (or a hack to fake it) or menu graphics will be missing
What happens is that it writes to cartridge ROM addresses and expects to be able to read back the written values, which works on actual hardware because the cache is write-through and the reads will hit in cache
Depends on the SH7604 division unit saturating quotients to signed 32-bit
Depends on emulating 68000 line 1010/1111 exceptions
Pushes the stack pointer onto the stack using mov.l r15, @-r15 instructions and depends on the original R15 value being written to memory, not the decremented R15 value
Sound effects depend on the PWM timer interval bits in $A15130 being read-only for the 68000; otherwise it will incorrectly change the timer interrupt interval from 1 to 16 which breaks nearly all sound effects
Uses different PWM sample rates for different sound effects