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Set default check register for shared interrupts (IDFGH-14469) #15243

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Set default check register for shared interrupts (IDFGH-14469) #15243

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14 changes: 13 additions & 1 deletion components/esp_hw_support/intr_alloc.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -23,6 +23,11 @@
#include "esp_cpu.h"
#include "esp_private/rtc_ctrl.h"
#include "soc/interrupts.h"
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#else
#include "soc/interrupt_reg.h"
#endif
#include "soc/soc_caps.h"
#include "sdkconfig.h"

Expand Down Expand Up @@ -576,6 +581,13 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
return ESP_ERR_NO_MEM;
}
memset(sh_vec, 0, sizeof(shared_vector_desc_t));
//If the shared interrupt does not have a register set for judgment, the corresponding source interrupt status is checked by default.
if(intrstatusreg == 0){
uint32_t offset = source / 32;
uint32_t source_bit = source % 32;
intrstatusreg = INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) + (offset * 4);
intrstatusmask = 1 << source_bit;
}
sh_vec->statusreg = (uint32_t*)intrstatusreg;
sh_vec->statusmask = intrstatusmask;
sh_vec->isr = handler;
Expand Down
8 changes: 7 additions & 1 deletion components/soc/esp32/register/soc/dport_reg.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -4286,3 +4286,9 @@
#define TRACEMEM_MUX_BLK0_ONLY 1
#define TRACEMEM_MUX_BLK1_ONLY 2
#define TRACEMEM_MUX_PROBLK1_APPBLK0 3

#if (!CONFIG_FREERTOS_UNICORE)
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) (cpu == 0? DPORT_PRO_INTR_STATUS_0_REG : DPORT_APP_INTR_STATUS_0_REG)
#else
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) DPORT_PRO_INTR_STATUS_0_REG
#endif
1 change: 1 addition & 0 deletions components/soc/esp32c2/include/soc/interrupt_reg.h
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Expand Up @@ -9,3 +9,4 @@

#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INTR_STATUS_REG_0_REG
1 change: 1 addition & 0 deletions components/soc/esp32c3/include/soc/interrupt_reg.h
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Expand Up @@ -9,3 +9,4 @@

#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INTR_STATUS_0_REG
3 changes: 3 additions & 0 deletions components/soc/esp32c5/include/soc/interrupt_reg.h
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Expand Up @@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/

#include "soc/interrupt_matrix_reg.h"
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"

Expand All @@ -19,6 +20,8 @@ extern "C" {
/* We only have a single core on the C5, CORE0 */
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG

#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INT_STATUS_0_REG

#ifdef __cplusplus
}
#endif
1 change: 0 additions & 1 deletion components/soc/esp32c5/register/soc/interrupt_matrix_reg.h
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Expand Up @@ -5,7 +5,6 @@
*/
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
Expand Down
1 change: 1 addition & 0 deletions components/soc/esp32c6/include/soc/interrupt_reg.h
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Expand Up @@ -43,3 +43,4 @@
#endif

#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTMTX_CORE0_INT_STATUS_REG_0_REG
3 changes: 3 additions & 0 deletions components/soc/esp32c61/include/soc/interrupt_reg.h
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Expand Up @@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/

#include "soc/interrupt_matrix_reg.h"
#include "soc/soc_caps.h"
#include "soc/clic_reg.h"

Expand All @@ -16,3 +17,5 @@
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG

#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE

#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INT_STATUS_0_REG
1 change: 0 additions & 1 deletion components/soc/esp32c61/register/soc/interrupt_matrix_reg.h
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Expand Up @@ -5,7 +5,6 @@
*/
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
Expand Down
1 change: 1 addition & 0 deletions components/soc/esp32h2/include/soc/interrupt_reg.h
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Expand Up @@ -22,3 +22,4 @@
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTMTX_CORE0_INT_STATUS_REG_0_REG
1 change: 1 addition & 0 deletions components/soc/esp32h21/register/soc/interrupt_reg.h
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Expand Up @@ -22,3 +22,4 @@
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTMTX_CORE0_INT_STATUS_REG_0_REG
10 changes: 9 additions & 1 deletion components/soc/esp32p4/include/soc/interrupt_reg.h
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@@ -1,10 +1,12 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

#include "soc/interrupt_core0_reg.h"
#include "soc/interrupt_core1_reg.h"
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"

Expand All @@ -25,6 +27,12 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (rv_utils_get_core_id() == 0 ? INTERRUPT_CURRENT_CORE_INT_THRESH_REG : INTERRUPT_OTHER_CORE_INT_THRESH_REG)
#define INTERRUPT_CORE1_CPU_INT_THRESH_REG (rv_utils_get_core_id() == 1 ? INTERRUPT_CURRENT_CORE_INT_THRESH_REG : INTERRUPT_OTHER_CORE_INT_THRESH_REG)

#if (!CONFIG_FREERTOS_UNICORE)
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) (cpu == 0? INTERRUPT_CORE0_INTR_STATUS_REG_0_REG : INTERRUPT_CORE1_INTR_STATUS_REG_0_REG)
#else
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INTR_STATUS_REG_0_REG
#endif

#ifdef __cplusplus
}
#endif
1 change: 0 additions & 1 deletion components/soc/esp32p4/register/soc/interrupt_core0_reg.h
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Expand Up @@ -5,7 +5,6 @@
*/
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
Expand Down
1 change: 0 additions & 1 deletion components/soc/esp32p4/register/soc/interrupt_core1_reg.h
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Expand Up @@ -5,7 +5,6 @@
*/
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
Expand Down
2 changes: 2 additions & 0 deletions components/soc/esp32s2/register/soc/interrupt_reg.h
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Expand Up @@ -809,6 +809,8 @@ extern "C" {
#define INTERRUPT_DATE_V 0xFFFFFFF
#define INTERRUPT_DATE_S 0

#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) DPORT_PRO_INTR_STATUS_0_REG

#ifdef __cplusplus
}
#endif
Expand Down
8 changes: 7 additions & 1 deletion components/soc/esp32s3/include/soc/interrupt_reg.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -11,6 +11,12 @@
#include "soc/interrupt_core1_reg.h"
#include "soc.h"

#if (!CONFIG_FREERTOS_UNICORE)
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) (cpu == 0? INTERRUPT_CORE0_INTR_STATUS_0_REG : INTERRUPT_CORE1_INTR_STATUS_0_REG)
#else
#define INTERRUPT_COREx_INTR_STATUS_REG_BASE(cpu) INTERRUPT_CORE0_INTR_STATUS_0_REG
#endif

#ifdef __cplusplus
extern "C" {
#endif
Expand Down
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