Add RocketCore

README.md

@@ -232,6 +232,43 @@ If using clion,
 $ nix develop .#t1.<config-name>.ip.emu -c clion ipemu/csrc
 ```
 
+#### Rocket emulator
+
+Rocket emulator contains multiple build phrase: RTL -> MLIR Bytecode ->
+system verilog -> verilated C sources -> Rust emulator.
+
+Most of the developer doesn't need to care about MLIR, system verilog and verilate detail.
+To develop the Rocket-chip RTL, run:
+
+```bash
+# This command provide a environment that contains mill, circt, espresso... development tools.
+nix develop '.#t1.elaborator'
+```
+
+> Metals LSP users are recommended to switch to mill-bsp mode instead of the default bloop mode.
+
+To elaborate the RTLs, run mill or use the nix chroot:
+
+```bash
+# for development
+mill -i elaborator.runMain org.chipsalliance.t1.elaborator.Main
+# for clean build
+nix build .#t1.rocketv-mlirbc
+```
+
+To develop the emulator, use the below nix environment:
+
+```bash
+nix develop .#t1.rocketv-emu.driver.devShell
+```
+
+This will setup the verilated C src in environment, download rust-analyzer.
+
+```bash
+cd rocketemu/driver
+cargo build --release
+```
+
 #### Developing Testcases
 The `tests/` contains the testcases. There are four types of testcases:
 

build.sc

@@ -35,7 +35,7 @@ trait Chisel
 
 object arithmetic extends Arithmetic
 
-trait Arithmetic 
+trait Arithmetic
   extends millbuild.dependencies.arithmetic.common.ArithmeticModule {
   override def millSourcePath = os.pwd / "dependencies" / "arithmetic" / "arithmetic"
   def scalaVersion = T(v.scala)
@@ -118,6 +118,23 @@ trait ConfigGen
   def mainargsIvy = v.mainargs
 }
 
+object rocketv extends RocketV
+
+trait RocketV
+  extends millbuild.common.RocketVModule
+    with ScalafmtModule {
+  def scalaVersion = T(v.scala)
+  def rvdecoderdbModule = rvdecoderdb
+  def riscvOpcodesPath = T.input(PathRef(os.pwd / "dependencies" / "riscv-opcodes"))
+  def hardfloatModule = hardfloat
+  def axi4Module = axi4
+
+  def chiselModule = Some(chisel)
+  def chiselPluginJar = T(Some(chisel.pluginModule.jar()))
+  def chiselPluginIvy = None
+  def chiselIvy = None
+}
+
 object ipemu extends IPEmulator
 
 trait IPEmulator
@@ -132,6 +149,18 @@ trait IPEmulator
   def chiselIvy = None
 }
 
+object rocketemu extends RocketEmulator
+trait RocketEmulator extends millbuild.common.RocketEmulatorModule {
+  def scalaVersion = T(v.scala)
+
+  def rocketVModule = rocketv
+
+  def chiselModule = Some(chisel)
+  def chiselPluginJar = T(Some(chisel.pluginModule.jar()))
+  def chiselPluginIvy = None
+  def chiselIvy = None
+}
+
 object panamaconverter extends PanamaConverter
 
 trait PanamaConverter
@@ -157,6 +186,8 @@ trait Elaborator
   def generators = Seq(
     t1,
     ipemu,
+    rocketv,
+    rocketemu,
   )
 
   def mainargsIvy = v.mainargs

common.sc

@@ -70,6 +70,30 @@ trait ConfigGenModule
   override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
 }
 
+// T1 forked version of RocketCore
+trait RocketModule
+  extends ScalaModule
+    with HasChisel
+    with HasRVDecoderDB {
+  def rocketchipModule: ScalaModule
+  def moduleDeps = super.moduleDeps ++ Seq(rocketchipModule)
+}
+
+// The next generation of purely standalone Rocket Core w/ AXI/CHI.
+trait RocketVModule
+  extends ScalaModule
+    with HasChisel
+    with HasRVDecoderDB {
+  def axi4Module: ScalaModule
+  def hardfloatModule: ScalaModule
+
+  def moduleDeps = super.moduleDeps ++ Seq(axi4Module, hardfloatModule)
+}
+
+trait EmuHelperModule
+  extends ScalaModule
+    with HasChisel
+
 trait IPEmulatorModule
   extends ScalaModule
     with HasChisel {
@@ -120,3 +144,10 @@ trait OMReaderModule
     super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
   )
 }
+
+trait RocketEmulatorModule
+  extends ScalaModule
+    with HasChisel {
+  def rocketVModule: ScalaModule
+  def moduleDeps = super.moduleDeps ++ Seq(rocketVModule)
+}

elaborator/src/Elaborator.scala

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <[email protected]>
+package org.chipsalliance.t1.elaborator
+
+import chisel3.RawModule
+import chisel3.experimental.{SerializableModule, SerializableModuleGenerator, SerializableModuleParameter}
+import mainargs.TokensReader
+
+import scala.reflect.runtime.universe
+import scala.reflect.runtime.universe.{runtimeMirror, typeOf}
+
+// TODO: this will be upstreamed to Chisel
+trait Elaborator {
+  implicit object PathRead extends TokensReader.Simple[os.Path] {
+    def shortName = "path"
+    def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd))
+  }
+
+  def configImpl[P <: SerializableModuleParameter: universe.TypeTag](
+                                                                      parameter: P
+                                                                    )(implicit rwP: upickle.default.Writer[P]) = os.write.over(
+    os.pwd / s"${getClass.getSimpleName.replace("$", "")}.json",
+    upickle.default.write(parameter)
+  )
+
+  def designImpl[
+    M <: SerializableModule[P]: universe.TypeTag,
+    P <: SerializableModuleParameter: universe.TypeTag
+  ](parameter: os.Path, runFirtool: Boolean)(implicit
+                                             rwP: upickle.default.Reader[P]
+  ) = {
+    var fir: firrtl.ir.Circuit = null
+    val annos = Seq(
+      new chisel3.stage.phases.Elaborate,
+      new chisel3.stage.phases.Convert
+    ).foldLeft(
+        Seq(
+          chisel3.stage.ChiselGeneratorAnnotation(() =>
+            SerializableModuleGenerator(
+              runtimeMirror(getClass.getClassLoader)
+                .runtimeClass(typeOf[M].typeSymbol.asClass)
+                .asInstanceOf[Class[M]],
+              upickle.default.read[P](os.read(parameter))
+            ).module().asInstanceOf[RawModule]
+          )
+        ): firrtl.AnnotationSeq
+      ) { case (annos, stage) => stage.transform(annos) }
+      .flatMap {
+        case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
+          fir = circuit
+          None
+        case _: chisel3.stage.DesignAnnotation[_]     => None
+        case _: chisel3.stage.ChiselCircuitAnnotation => None
+        case a                                        => Some(a)
+      }
+    val annoJsonFile = os.pwd / s"${fir.main}.anno.json"
+    val firFile = os.pwd / s"${fir.main}.fir"
+    val svFile = os.pwd / s"${fir.main}.sv"
+    os.write.over(firFile, fir.serialize)
+    os.write.over(
+      annoJsonFile,
+      firrtl.annotations.JsonProtocol.serializeRecover(annos)
+    )
+    if (runFirtool) {
+      os.proc(
+        "firtool",
+        s"--annotation-file=${annoJsonFile}",
+        s"${firFile}",
+        s"-o",
+        s"${svFile}",
+        "--strip-debug-info",
+        "--verification-flavor=sva",
+        "--extract-test-code"
+      ).call(os.pwd)
+    }
+  }
+}

elaborator/src/Main.scala

@@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator
 
 import mainargs._
 import org.chipsalliance.t1.rtl.T1Parameter
+import org.chipsalliance.rocketv.RocketTileParameter
 import chisel3.panamalib.option._
 
 object Main {
@@ -66,7 +67,15 @@ object Main {
     def parameter: T1Parameter = generator.parameter
   }
 
+  case class RocketConfig(
+    @arg(name = "rocket-config", short = 'c') rocketConfig: os.Path) {
+    def generator = upickle.default
+      .read[chisel3.experimental.SerializableModuleGenerator[org.chipsalliance.rocketv.RocketTile, org.chipsalliance.rocketv.RocketTileParameter]](ujson.read(os.read(rocketConfig)))
+    def parameter: RocketTileParameter = generator.parameter
+  }
+
   implicit def ipConfig: ParserForClass[IPConfig] = ParserForClass[IPConfig]
+  implicit def rocketConfig: ParserForClass[RocketConfig] = ParserForClass[RocketConfig]
 
   // format: off
   @main def ip(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit = elaborateConfig.elaborate(() =>
@@ -75,6 +84,9 @@ object Main {
   @main def ipemu(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit = elaborateConfig.elaborate(() =>
     new org.chipsalliance.t1.ipemu.TestBench(ipConfig.generator)
   )
+  @main def rocketemu(elaborateConfig: ElaborateConfig, rocketConfig: RocketConfig): Unit = elaborateConfig.elaborate(() =>
+    new org.chipsalliance.t1.rocketv.TestBench(rocketConfig.generator)
+  )
   // format: on
 
   def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)

elaborator/src/rocketv/ALU.scala

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <[email protected]>
+package org.chipsalliance.t1.elaborator.rocketv
+
+import mainargs._
+import org.chipsalliance.rocketv.{ALU, ALUParameter}
+import org.chipsalliance.t1.elaborator.Elaborator
+
+object ALU extends Elaborator {
+  @main
+  case class ALUParameterMain(
+    @arg(name = "xLen") xLen: Int) {
+    def convert: ALUParameter = ALUParameter(xLen)
+  }
+
+  implicit def ALUParameterMainParser: ParserForClass[ALUParameterMain] = ParserForClass[ALUParameterMain]
+
+  @main
+  def config(@arg(name = "parameter") parameter: ALUParameterMain) = configImpl(parameter.convert)
+
+  @main
+  def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) =
+    designImpl[ALU, ALUParameter](parameter, runFirtool.value)
+
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+}

elaborator/src/rocketv/AMOALU.scala

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <[email protected]>
+package org.chipsalliance.t1.elaborator.rocketv
+
+import mainargs._
+import org.chipsalliance.rocketv.{AMOALU, AMOALUParameter}
+import org.chipsalliance.t1.elaborator.Elaborator
+
+object AMOALU extends Elaborator {
+  @main
+  case class AMOALUParameterMain(
+    @arg(name = "operandBits") operandBits: Int) {
+    def convert: AMOALUParameter = AMOALUParameter(operandBits)
+  }
+
+  implicit def AMOALUParameterMainParser: ParserForClass[AMOALUParameterMain] = ParserForClass[AMOALUParameterMain]
+
+  @main
+  def config(@arg(name = "parameter") parameter: AMOALUParameterMain) = configImpl(parameter.convert)
+
+  @main
+  def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) =
+    designImpl[AMOALU, AMOALUParameter](parameter, runFirtool.value)
+
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+}

elaborator/src/rocketv/BTB.scala

@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2024 Jiuyang Liu <[email protected]>
+package org.chipsalliance.t1.elaborator.rocketv
+
+import mainargs._
+import org.chipsalliance.rocketv.{BHTParameter, BTB, BTBParameter}
+import org.chipsalliance.t1.elaborator.Elaborator
+
+object BTB extends Elaborator {
+  @main
+  case class BHTParameterMain(
+    @arg(name = "nEntries") nEntries:           Int,
+    @arg(name = "counterLength") counterLength: Int,
+    @arg(name = "historyLength") historyLength: Int,
+    @arg(name = "historyBits") historyBits:     Int) {
+    def convert: BHTParameter = BHTParameter(
+      nEntries,
+      counterLength,
+      historyLength,
+      historyBits
+    )
+  }
+  implicit def BHTParameterMainParser: ParserForClass[BHTParameterMain] = ParserForClass[BHTParameterMain]
+
+  @main
+  case class BTBParameterMain(
+    @arg(name = "useAsyncReset") useAsyncReset:         Boolean,
+    @arg(name = "fetchBytes") fetchBytes:               Int,
+    @arg(name = "vaddrBits") vaddrBits:                 Int,
+    @arg(name = "entries") entries:                     Int,
+    @arg(name = "nMatchBits") nMatchBits:               Int,
+    @arg(name = "nPages") nPages:                       Int,
+    @arg(name = "nRAS") nRAS:                           Int,
+    @arg(name = "cacheBlockBytes") cacheBlockBytes:     Int,
+    @arg(name = "iCacheSet") iCacheSet:                 Int,
+    @arg(name = "useCompressed") useCompressed:         Boolean,
+    @arg(name = "updatesOutOfOrder") updatesOutOfOrder: Boolean,
+    @arg(name = "bht-nEntries") nEntries:               Option[Int],
+    @arg(name = "bht-counterLength") counterLength:     Option[Int],
+    @arg(name = "bht-historyLength") historyLength:     Option[Int],
+    @arg(name = "bht-historyBits") historyBits:         Option[Int],
+    @arg(name = "fetchWidth") fetchWidth:               Int,
+                             ) {
+    def convert: BTBParameter = BTBParameter(
+      useAsyncReset,
+      fetchBytes,
+      vaddrBits,
+      entries,
+      nMatchBits,
+      nPages,
+      nRAS,
+      cacheBlockBytes,
+      iCacheSet,
+      useCompressed,
+      updatesOutOfOrder,
+      fetchWidth,
+      (nEntries
+        .lazyZip(counterLength)
+        .lazyZip(historyLength)
+        .lazyZip(historyBits))
+        .map {
+          case (nEntries, counterLength, historyLength, historyBits) =>
+            BHTParameter(nEntries, counterLength, historyLength, historyBits)
+        }
+        .headOption
+    )
+  }
+
+  implicit def BTBParameterMainParser: ParserForClass[BTBParameterMain] = ParserForClass[BTBParameterMain]
+
+  @main
+  def config(@arg(name = "parameter") parameter: BTBParameterMain) = configImpl(parameter.convert)
+
+  @main
+  def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) =
+    designImpl[BTB, BTBParameter](parameter, runFirtool.value)
+
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+}