Add RocketCore #705
Merged
Add RocketCore #705
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
sequencer
force-pushed
the
jiuyang/real-rocket-v
branch
from
63117be to
dca9103
Compare
Clo91eaf
force-pushed
the
jiuyang/real-rocket-v
branch
from
dca9103 to
118f4ad
Compare
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU config --xLen 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU design --parameter ./ALU.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU config --operandBits 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU design --parameter ./AMOALU.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit config --nBreakpoints 4 --xLen 32 --useBPWatch true --vaddrBits 32 --mcontextWidth 0 --scontextWidth 0 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit design --parameter ./BreakpointUnit.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB config --useAsyncReset true --fetchBytes 16 --vaddrBits 34 --entries 28 --nMatchBits 14 --nPages 6 --nRAS 6 --cacheBlockBytes 64 --iCacheSet 64 --useCompressed true --updatesOutOfOrder false --bht-nEntries 512 --bht-counterLength 1 --bht-historyLength 8 --bht-historyBits 3 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB design --parameter ./BTB.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR config --vLen 512 --useAsyncReset false --xLen 32 --fLen 32 --usingSupervisor false --usingFPU true --usingUser false --usingVM false --pgLevels 2 --hartIdLen 1 --usingCompressed true --usingAtomics true --usingDebug true --usingMulDiv true --usingVector true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR design --parameter ./CSR.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder config --pipelinedMul false --fenceIFlushDCache false --instructionSets rv32_i --instructionSets rv_v - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder design --parameter ./Decoder.json --run-firtool
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander config --xLen 32 --usingCompressed true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander design --parameter ./RVCExpander.json --run-firtool
This commit keep AXI agent implementation in sync with the axi4-t1 branch, with ClockGen and DumpWave module embedded inside the TestBench module. Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
[rocketemu] fix wrong exit macro [rocketemu] fix wrong sw format [nix] use t1-env for riscv-tests [tests] fix MMIO write when exit [rocketemu] remove ecall
Signed-off-by: Avimitin <[email protected]>
[rocketemu] catch watchdog timeout event in offline difftest [rocketemu] optimize difftest loop [rocketemu] should not soft link the nix result directly [rocketemu] spike event record reg write idx with hex [rocketemu] add support for msu priviledge [rocketemu] skip check when spike/rtl reg write idx == 0
Signed-off-by: Avimitin <[email protected]>
Signed-off-by: Avimitin <[email protected]>
sequencer
force-pushed
the
jiuyang/real-rocket-v
branch
from
118f4ad to
e9ec3b0
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR will adds the AXI4 version of Rocket, but eventually will be moved to chipsalliance/rocket