#5 - Wire index optional

src/circuit.rs

@@ -1,7 +1,7 @@
+use std::cell::RefCell;
 use std::collections::BTreeMap;
 use std::iter::zip;
 use std::rc::Rc;
-use std::cell::RefCell;
 
 use crate::utils::read_lines;
 use crate::{
@@ -110,8 +110,7 @@ impl CircuitTrait for Circuit {
                     let output_wires = (0..noo)
                         .map(|_| {
                             let k = words.next().unwrap().parse::<usize>().unwrap();
-                            let x = wire_indices
-                                .get(&k).unwrap().clone();
+                            let x = wire_indices.get(&k).unwrap().clone();
                             x
                         })
                         .collect();
@@ -151,7 +150,10 @@ impl CircuitTrait for Circuit {
             input_sizes,
             output_sizes,
             gates,
-            wires: wire_indices.values().cloned().collect::<Vec<Rc<RefCell<Wire>>>>(),
+            wires: wire_indices
+                .values()
+                .cloned()
+                .collect::<Vec<Rc<RefCell<Wire>>>>(),
         };
     }
 
@@ -161,7 +163,7 @@ impl CircuitTrait for Circuit {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use crate::utils::{number_to_bool_array, bool_array_to_number};
+    use crate::utils::{bool_array_to_number, number_to_bool_array};
 
     #[test]
     fn test_circuit() {

src/gates.rs

@@ -1,6 +1,6 @@
 use crate::{traits::gate::GateTrait, wire::Wire};
-use std::rc::Rc;
 use std::cell::RefCell;
+use std::rc::Rc;
 
 // Every gate has a type parameter COM, which is a bit commitment scheme which can be hash based or schnorr based.
 // Every gate has an array of input wire pointers.
@@ -39,7 +39,10 @@ impl GateTrait for NotGate {
     }
 
     fn print(&self) -> String {
-        format!("Gate[]: {:?}, {:?}, {:?}", self.input_wires[0], self.input_wires[1], self.output_wires[0])
+        format!(
+            "Gate[]: {:?}, {:?}, {:?}",
+            self.input_wires[0], self.input_wires[1], self.output_wires[0]
+        )
     }
 }
 
@@ -72,12 +75,13 @@ impl GateTrait for AndGate {
         out.selector = Some(w);
     }
 
-    fn set_input_wires(&mut self) {
-
-    }
+    fn set_input_wires(&mut self) {}
 
     fn print(&self) -> String {
-        format!("Gate[]: {:?}, {:?}, {:?}", self.input_wires[0], self.input_wires[1], self.output_wires[0])
+        format!(
+            "Gate[]: {:?}, {:?}, {:?}",
+            self.input_wires[0], self.input_wires[1], self.output_wires[0]
+        )
     }
 }
 
@@ -110,11 +114,12 @@ impl GateTrait for XorGate {
         out.selector = Some(w);
     }
 
-    fn set_input_wires(&mut self) {
-
-    }
+    fn set_input_wires(&mut self) {}
 
     fn print(&self) -> String {
-        format!("Gate[]: {:?}, {:?}, {:?}", self.input_wires[0], self.input_wires[1], self.output_wires[0])
+        format!(
+            "Gate[]: {:?}, {:?}, {:?}",
+            self.input_wires[0], self.input_wires[1], self.output_wires[0]
+        )
     }
 }

src/main.rs

@@ -1,5 +1,5 @@
+use bitvmrs::utils::{bool_array_to_number, number_to_bool_array};
 use bitvmrs::{circuit::Circuit, traits::circuit::CircuitTrait};
-use bitvmrs::utils::{number_to_bool_array, bool_array_to_number};
 
 fn main() {
     println!("Hello, world!");

src/traits/gate.rs

@@ -8,4 +8,3 @@ pub trait GateTrait {
     fn set_input_wires(&mut self);
     fn print(&self) -> String;
 }
-