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SPI Engine: simplify interconnect #1502

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SPI Engine: simplify interconnect #1502

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d845ac3
SPI Engine: decouple SDO data handshake from control
LBFFilho Sep 6, 2024
c504d82
projects/ad4052/de10nano: update required quartus version
LBFFilho Jan 17, 2025
a87a4c6
Update license headers for 2025
LBFFilho Jan 17, 2025
61558f3
ad4052/cora: Update impl strategy for timing closure
sarpadi Jan 21, 2025
9102371
SPI Engine: simplify interconnect
LBFFilho Oct 11, 2024
79cd8ea
axi_ad5766: add interconnect control
LBFFilho Oct 29, 2024
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6 changes: 3 additions & 3 deletions docs/regmap/adi_regmap_spi_engine.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ ENDTITLE
REG
0x00
VERSION
Version of the peripheral. Follows semantic versioning. Current version 1.03.01.
Version of the peripheral. Follows semantic versioning. Current version 1.04.01.
ENDREG

FIELD
Expand All @@ -19,13 +19,13 @@ RO
ENDFIELD

FIELD
[15:8] 0x00000003
[15:8] 0x00000004
VERSION_MINOR
RO
ENDFIELD

FIELD
[7:0] 0x00000001
[7:0] 0x00000000
VERSION_PATCH
RO
ENDFIELD
Expand Down
4 changes: 3 additions & 1 deletion library/axi_ad5766/Makefile
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@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
Expand All @@ -22,6 +22,8 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl_rtl.xml

XILINX_LIB_DEPS += util_cdc

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11 changes: 9 additions & 2 deletions library/axi_ad5766/axi_ad5766.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -112,7 +112,11 @@ module axi_ad5766 #(

input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset
input ctrl_mem_reset,

// SPI engine interconnect interface

output interconnect_dir
);

// internal wires
Expand Down Expand Up @@ -186,6 +190,8 @@ module axi_ad5766 #(
wire ctrl_is_enabled;
reg spi_enabled = 1'b0;

assign interconnect_dir = spi_enabled;

always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
Expand Down Expand Up @@ -231,6 +237,7 @@ module axi_ad5766 #(
assign spi_enable_s = ctrl_enable;
assign ctrl_enabled = spi_enable_s | spi_active;
assign spi_mem_reset_s = ctrl_mem_reset;
assign interconnect_dir = ctrl_enabled;
end endgenerate

assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
Expand Down
10 changes: 9 additions & 1 deletion library/axi_ad5766/axi_ad5766_ip.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -62,9 +62,17 @@ adi_add_bus "spi_engine_offload_ctrl" "slave" \
{ "status_sync_data" "sync_data"} \
}

adi_add_bus "m_interconnect_ctrl" "master" \
"analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_interconnect_ctrl:1.0" \
{ \
{"interconnect_dir" "interconnect_dir"} \
}

adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
adi_add_bus_clock "dma_clk" "dma_fifo_tx"
adi_add_bus_clock "spi_clk" "m_interconnect_ctrl" "resetn"

adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
Expand Down
4 changes: 2 additions & 2 deletions library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -133,7 +133,7 @@ module axi_spi_engine #(
input [7:0] offload_sync_data
);

localparam PCORE_VERSION = 'h010301;
localparam PCORE_VERSION = 'h010401;
localparam S_AXI = 0;
localparam UP_FIFO = 1;

Expand Down
4 changes: 3 additions & 1 deletion library/spi_engine/interfaces/Makefile
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
####################################################################################
####################################################################################
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
Expand All @@ -18,6 +18,8 @@ XML_FLIST += spi_engine_ctrl.xml
XML_FLIST += spi_engine_ctrl_rtl.xml
XML_FLIST += spi_engine_offload_ctrl.xml
XML_FLIST += spi_engine_offload_ctrl_rtl.xml
XML_FLIST += spi_engine_interconnect_ctrl.xml
XML_FLIST += spi_engine_interconnect_ctrl_rtl.xml

M_FLIST := *.log
M_FLIST += *.jou
Expand Down
7 changes: 6 additions & 1 deletion library/spi_engine/interfaces/interfaces_ip.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -45,3 +45,8 @@ adi_if_ports input 1 enabled
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data

# Interconnect control interface

adi_if_define "spi_engine_interconnect_ctrl"
adi_if_ports output 1 interconnect_dir
3 changes: 2 additions & 1 deletion library/spi_engine/scripts/spi_engine.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -63,6 +63,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi

ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
ad_connect $interconnect/m_ctrl $execution/ctrl
Expand Down
24 changes: 11 additions & 13 deletions library/spi_engine/spi_engine_execution/spi_engine_execution.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -132,6 +132,8 @@ module spi_engine_execution #(

reg sdo_enabled = 1'b0;
reg sdi_enabled = 1'b0;
wire sdo_enabled_io;
wire sdi_enabled_io;

wire sdo_int_s;

Expand Down Expand Up @@ -165,7 +167,7 @@ module spi_engine_execution #(

wire end_of_sdi_latch;

wire sample_sdo;
wire sdo_io_ready;

(* direct_enable = "yes" *) wire cs_gen;

Expand Down Expand Up @@ -194,7 +196,6 @@ module spi_engine_execution #(
.sdo_idle_state(sdo_idle_state),
.left_aligned(left_aligned),
.word_length(word_length),
.sample_sdo(sample_sdo),
.sdo_io_ready(sdo_io_ready),
.transfer_active(transfer_active),
.trigger_tx(trigger_tx),
Expand All @@ -203,8 +204,6 @@ module spi_engine_execution #(
.cs_activate(cs_activate),
.end_of_sdi_latch(end_of_sdi_latch));

assign sample_sdo = sdo_data_valid && ((trigger_tx && last_bit) || (wait_for_io || exec_transfer_cmd));

assign cs_gen = inst_d1 == CMD_CHIPSELECT
&& ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit)
&& (cs_sleep_repeat == 1'b0)
Expand All @@ -217,6 +216,8 @@ module spi_engine_execution #(
sdi_enabled <= cmd[9];
end
end
assign sdo_enabled_io = (exec_transfer_cmd) ? cmd[8] : sdo_enabled;
assign sdi_enabled_io = (exec_transfer_cmd) ? cmd[9] : sdi_enabled;

always @(posedge clk) begin
if (cmd_ready & cmd_valid)
Expand Down Expand Up @@ -388,9 +389,9 @@ module spi_engine_execution #(
assign sync = cmd_d1[7:0];

assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_io_ready == 1'b1);
(sdo_enabled_io == 1'b0 || sdo_io_ready == 1'b1);
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
(sdo_enabled_io == 1'b0 || last_transfer == 1'b1 || sdo_io_ready == 1'b1);

always @(posedge clk) begin
if (idle == 1'b1) begin
Expand All @@ -409,14 +410,11 @@ module spi_engine_execution #(
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
wait_for_io <= !io_ready1;
transfer_active <= io_ready1;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
transfer_active <= !last_transfer;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
Expand Down
48 changes: 23 additions & 25 deletions library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -55,7 +55,7 @@ module spi_engine_execution_shiftreg #(
// spi data
input [(DATA_WIDTH-1):0] sdo_data,
input sdo_data_valid,
output reg sdo_data_ready,
output sdo_data_ready,

output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output reg sdi_data_valid,
Expand All @@ -70,8 +70,7 @@ module spi_engine_execution_shiftreg #(
input [ 7:0] word_length,

// timing from main fsm
input sample_sdo,
output reg sdo_io_ready,
output sdo_io_ready,
input transfer_active,
input trigger_tx,
input trigger_rx,
Expand All @@ -83,36 +82,35 @@ module spi_engine_execution_shiftreg #(
reg [ 7:0] sdi_counter = 8'b0;
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [ SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_d;

wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];
wire last_sdi_bit;

always @(posedge clk) begin
reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_reg;
reg data_sdo_v;
wire sdo_toshiftreg;
wire last_sdi_bit;
wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];

// sdo data handshake
assign sdo_data_ready = (!data_sdo_v) || sdo_toshiftreg;
assign sdo_io_ready = data_sdo_v;
always @(posedge clk ) begin
if (resetn == 1'b0) begin
sdo_data_ready <= 1'b0;
end else if (sdo_toshiftreg) begin
sdo_data_ready <= 1'b1;
end else if (sdo_data_valid == 1'b1) begin
sdo_data_ready <= 1'b0;
data_sdo_v <= 1'b0;
end else begin
if (sdo_data_ready && sdo_data_valid) begin
data_sdo_v <= 1'b1;
sdo_data_reg <= sdo_data;
end else if (sdo_toshiftreg) begin
data_sdo_v <= 1'b0;
end
end
end

// pipelined shifter for sdo_data
always @(posedge clk ) begin
if (resetn == 1'b0) begin
aligned_sdo_data <= 0;
sdo_io_ready <= 1'b0;
end else begin
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
sdo_io_ready <= 1'b0;
end
if (sample_sdo) begin
sdo_data_d <= sdo_data;
sdo_io_ready <= 1'b1;
end
aligned_sdo_data <= sdo_data_d << left_aligned;
aligned_sdo_data <= sdo_data_reg << left_aligned;
end
end

Expand Down
4 changes: 3 additions & 1 deletion library/spi_engine/spi_engine_interconnect/Makefile
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
Expand All @@ -12,6 +12,8 @@ XILINX_DEPS += spi_engine_interconnect_ip.tcl

XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl_rtl.xml

XILINX_INTERFACE_DEPS += spi_engine/interfaces

Expand Down
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