SPI Engine: simplify interconnect #1502
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SDO data can now be clocked in independently from the offload trigger. This allows lower latencies for executing transfers, since the data can be obtained from the DMA before the trigger. It also better separates the command path from the data path. SDO data source behavior is altered: previously, with SDO_STREAMING=1 the SPI Engine would prioritize the SDO memory and switch to AXI Streaming when empty. This unused automatic switching is now removed: if the SPI Engine is built with SDO_STREAMING=1 it will only get SDO data from AXI Streaming, and with SDO_STREAMING=0 it will only use the SDO memory. Signed-off-by: Laez Barbosa <[email protected]>
Make the interconnect use an external signal for switching between sources, so it becomes just a collection of muxes, reducing latency. This signal is generated based on the software-controlled offload enable, but is sourced from the offload module to avoid unnecessary CDCs. This commit makes the use of SYNC optional. Signed-off-by: Laez Barbosa <[email protected]>
Signed-off-by: Laez Barbosa <[email protected]>
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Tested with AD4052 |
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PR Description
Simplifies the interconnect logic, which is now just a set of muxes controlled by a signal from the offload module.
This makes the SYNC instructions optional, and reduces the trigger to first instruction latency.
Since it acts as a substitute for the offload module, axi_ad5766 had to be updated as well in order for it to provide the same interconnect control signal.
(This PR should be merged after #1501)
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