RTLIL Module dump and hash

kernel/rtlil.cc

@@ -27,6 +27,10 @@
 #include "backends/rtlil/rtlil_backend.h"
 
 #include <string.h>
+#include <strstream>
+#include <unordered_map>
+#include <locale>
+#include <codecvt>
 #include <algorithm>
 #include <optional>
 
@@ -2508,6 +2512,28 @@ void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
 	wires_[w2->name] = w2;
 }
 
+// Returns the RTLIL dump of a module
+std::string RTLIL::Module::rtlil_dump() {
+	std::stringstream stream;
+	// Sorting the module to have a canonical RTLIL
+	sort();
+	// Dumping the RTLIL in an in-memory stringstream 
+	RTLIL_BACKEND::dump_module(stream, " ", this, design, false, true, false);
+	std::string origstring = stream.str();
+	//RTLIL contains non utf-8 characters, converting to utf-8
+	std::wstring_convert<std::codecvt_utf8<char32_t>, char32_t> converter;
+	std::u32string orig(origstring.begin(), origstring.end());
+	std::string utf8String = converter.to_bytes(orig);
+	return utf8String;
+}
+
+// Returns a hash of the RTLIL dump
+std::string RTLIL::Module::rtlil_hash() {
+	std::hash<std::string> hasher;
+	size_t hash = hasher(rtlil_dump());
+	return std::to_string(hash);
+}
+
 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
 {
 	log_assert(cells_[c1->name] == c1);

kernel/rtlil.h

@@ -1591,6 +1591,9 @@ struct RTLIL::Module : public RTLIL::AttrObject
 	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
 	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
 
+	std::string rtlil_dump();
+	std::string rtlil_hash();
+
 #ifdef WITH_PYTHON
 	static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
 #endif