Merge branch 'YosysHQ:main' into main

Makefile

@@ -162,7 +162,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.47+0
+YOSYS_VER := 0.47+3
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

kernel/fstdata.cc

@@ -137,14 +137,22 @@ void FstData::extractVarNames()
 				if (!var.is_alias)
 					handle_to_var[h->u.var.handle] = var;
 				std::string clean_name;
+				bool has_space = false;
 				for(size_t i=0;i<strlen(h->u.var.name);i++) 
 				{
 					char c = h->u.var.name[i];
-					if(c==' ') break;
+					if(c==' ') { has_space = true; break; }
 					clean_name += c;
 				}
 				if (clean_name[0]=='\\')
 					clean_name = clean_name.substr(1);
+				if (!has_space) {
+					size_t pos = clean_name.find_last_of("[");
+					std::string index_or_range = clean_name.substr(pos+1);
+					if (index_or_range.find(":") != std::string::npos) {
+						clean_name = clean_name.substr(0,pos);
+					}
+				}
 				size_t pos = clean_name.find_last_of("<");
 				if (pos != std::string::npos && clean_name.back() == '>') {
 					std::string mem_cell = clean_name.substr(0, pos);
@@ -258,7 +266,8 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
 
 std::string FstData::valueOf(fstHandle signal)
 {
-	if (past_data.find(signal) == past_data.end())
-		log_error("Signal id %d not found\n", (int)signal);
+	if (past_data.find(signal) == past_data.end()) {
+		return std::string(handle_to_var[signal].width, 'x');
+	}
 	return past_data[signal];
 }

tests/sim/assume_x_first_step.ys

@@ -0,0 +1,2 @@
+read_verilog simple_assign.v
+sim -r simple_assign.vcd -scope simple_assign

tests/sim/simple_assign.v

@@ -0,0 +1,8 @@
+module simple_assign (
+    input wire in,
+    output wire out
+);
+
+    assign out = in;
+
+endmodule

tests/sim/simple_assign.vcd

@@ -0,0 +1,13 @@
+$version Yosys $end
+$scope module simple_assign $end
+$var wire 1 n2 in $end
+$var wire 1 n1 out $end
+$upscope $end
+$enddefinitions $end
+#0
+#5
+b1 n1
+b1 n2
+#10
+b0 n1
+b0 n2

tests/sim/var_reference_with_whitespace.vcd

@@ -0,0 +1,28 @@
+$date
+  Fri Sep 27 11:58:46 2024
+$end
+$version
+  GHDL v0
+$end
+$timescale
+  1 fs
+$end
+$scope module standard $end
+$upscope $end
+$scope module std_logic_1164 $end
+$upscope $end
+$scope module tb $end
+$var reg 4 ! a [3:0] $end
+$var reg 4 " b [3:0] $end
+$scope module uut $end
+$var reg 4 # a [3:0] $end
+$var reg 4 $ b [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+b0001 !
+b0001 "
+b0001 #
+b0001 $
+#10000000

tests/sim/var_reference_without_whitespace.vcd

@@ -0,0 +1,28 @@
+$date
+  Fri Sep 27 11:58:46 2024
+$end
+$version
+  GHDL v0
+$end
+$timescale
+  1 fs
+$end
+$scope module standard $end
+$upscope $end
+$scope module std_logic_1164 $end
+$upscope $end
+$scope module tb $end
+$var reg 4 ! a[3:0] $end
+$var reg 4 " b[3:0] $end
+$scope module uut $end
+$var reg 4 # a[3:0] $end
+$var reg 4 $ b[3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+b0001 !
+b0001 "
+b0001 #
+b0001 $
+#10000000

tests/sim/vcd_var_reference_whitespace.ys

@@ -0,0 +1,3 @@
+read_rtlil vector_assign.il
+sim -r var_reference_without_whitespace.vcd -scope tb.uut
+sim -r var_reference_with_whitespace.vcd -scope tb.uut

tests/sim/vector_assign.il

@@ -0,0 +1,20 @@
+# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
+autoidx 2
+attribute \architecture "Behavioral"
+attribute \library "work"
+attribute \hdlname "vector_assign"
+attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
+module \vector_assign
+  attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
+  wire width 4 input 2 \a
+  attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
+  wire width 4 output 1 \b
+  attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
+  cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \a
+    connect \Y \b
+  end
+end