assembler-aarch32: Add support for emitting AES instructions

Adds support for emitting AESD, AESE, AESIMC, and AESMC
Linaro · Jan 26, 2022 · a850162 · a850162
1 parent b0cd67c
commit a850162
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Showing 4 changed files with 120 additions and 6 deletions.
diff --git a/src/aarch32/assembler-aarch32.cc b/src/aarch32/assembler-aarch32.cc
@@ -2694,6 +2694,94 @@ bool Assembler::adr_info(Condition cond,
   return false;
 }
 
+void Assembler::aesd(Condition cond, DataType dt, QRegister rd, QRegister rm) {
+  VIXL_ASSERT(AllowAssembler());
+  VIXL_ASSERT(dt.Is(Untyped8));
+  CheckIT(cond);
+
+  if (IsUsingT32()) {
+    // AESD{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
+    if (cond.Is(al) || AllowStronglyDiscouraged()) {
+      EmitT32_32(0xffb00340 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      AdvanceIT();
+      return;
+    }
+  } else {
+    // AESD{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
+    if (cond.Is(al)) {
+      EmitA32(0xf3b00340 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      return;
+    }
+  }
+  Delegate(kAesd, &Assembler::aesd, cond, dt, rd, rm);
+}
+
+void Assembler::aese(Condition cond, DataType dt, QRegister rd, QRegister rm) {
+  VIXL_ASSERT(AllowAssembler());
+  VIXL_ASSERT(dt.Is(Untyped8));
+  CheckIT(cond);
+
+  if (IsUsingT32()) {
+    // AESE{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
+    if (cond.Is(al) || AllowStronglyDiscouraged()) {
+      EmitT32_32(0xffb00300 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      AdvanceIT();
+      return;
+    }
+  } else {
+    // AESE{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
+    if (cond.Is(al)) {
+      EmitA32(0xf3b00300 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      return;
+    }
+  }
+  Delegate(kAese, &Assembler::aese, cond, dt, rd, rm);
+}
+
+void Assembler::aesimc(Condition cond, DataType dt, QRegister rd, QRegister rm) {
+  VIXL_ASSERT(AllowAssembler());
+  VIXL_ASSERT(dt.Is(Untyped8));
+  CheckIT(cond);
+
+  if (IsUsingT32()) {
+    // AESIMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
+    if (cond.Is(al) || AllowStronglyDiscouraged()) {
+      EmitT32_32(0xffb003c0 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      AdvanceIT();
+      return;
+    }
+  } else {
+    // AESIMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
+    if (cond.Is(al)) {
+      EmitA32(0xf3b003c0 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      return;
+    }
+  }
+  Delegate(kAesimc, &Assembler::aesimc, cond, dt, rd, rm);
+}
+
+void Assembler::aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm) {
+  VIXL_ASSERT(AllowAssembler());
+  VIXL_ASSERT(dt.Is(Untyped8));
+  CheckIT(cond);
+
+  if (IsUsingT32()) {
+    // AESMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; T1
+    if (cond.Is(al) || AllowStronglyDiscouraged()) {
+      EmitT32_32(0xffb00380 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      AdvanceIT();
+      return;
+    }
+  } else {
+    // AESMC{<c>}{<q>}.<dt> <Qd>, <Qm> ; A1
+    if (cond.Is(al)) {
+      EmitA32(0xf3b00380 | rd.Encode(22, 12) | rm.Encode(5, 0));
+      return;
+    }
+  }
+  Delegate(kAesmc, &Assembler::aesmc, cond, dt, rd, rm);
+}
+
 void Assembler::and_(Condition cond,
                      EncodingSize size,
                      Register rd,

diff --git a/src/aarch32/assembler-aarch32.h b/src/aarch32/assembler-aarch32.h
@@ -1161,12 +1161,14 @@ class Assembler : public internal::AssemblerBase {
                         QRegister /*rd*/,
                         QRegister /*rm*/) {
     USE(type);
-    VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) ||
-                (type == kVcnt) || (type == kVneg) || (type == kVpadal) ||
-                (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) ||
-                (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) ||
-                (type == kVrev64) || (type == kVrsqrte) || (type == kVswp) ||
-                (type == kVtrn) || (type == kVuzp) || (type == kVzip));
+    VIXL_ASSERT((type == kAesd) || (type == kAese) || (type == kAesimc) ||
+                (type == kAesimc) || (type == kVabs) || (type == kVcls) ||
+                (type == kVclz) || (type == kVcnt) || (type == kVneg) ||
+                (type == kVpadal) || (type == kVpaddl) || (type == kVqabs) ||
+                (type == kVqneg) || (type == kVrecpe) || (type == kVrev16) ||
+                (type == kVrev32) || (type == kVrev64) || (type == kVrsqrte) ||
+                (type == kVswp) || (type == kVtrn) || (type == kVuzp) ||
+                (type == kVzip));
     UnimplementedDelegate(type);
   }
   virtual void Delegate(InstructionType type,
@@ -1971,6 +1973,18 @@ class Assembler : public internal::AssemblerBase {
     adr(al, size, rd, location);
   }
 
+  void aesd(Condition cond, DataType dt, QRegister rd, QRegister rm);
+  void aesd(QRegister rd, QRegister rm) { aesd(al, Untyped8, rd, rm); }
+
+  void aese(Condition cond, DataType dt, QRegister rd, QRegister rm);
+  void aese(QRegister rd, QRegister rm) { aese(al, Untyped8, rd, rm); }
+
+  void aesimc(Condition cond, DataType dt, QRegister rd, QRegister rm);
+  void aesimc(QRegister rd, QRegister rm) { aesimc(al, Untyped8, rd, rm); }
+
+  void aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm);
+  void aesmc(QRegister rd, QRegister rm) { aesmc(al, Untyped8, rd, rm); }
+
   void and_(Condition cond,
             EncodingSize size,
             Register rd,

diff --git a/src/aarch32/constants-aarch32.cc b/src/aarch32/constants-aarch32.cc
@@ -46,6 +46,14 @@ const char* ToCString(InstructionType type) {
       return "addw";
     case kAdr:
       return "adr";
+    case kAesd:
+      return "aesd";
+    case kAese:
+      return "aese";
+    case kAesimc:
+      return "aesimc";
+    case kAesmc:
+      return "aesmc";
     case kAnd:
       return "and";
     case kAnds:

diff --git a/src/aarch32/constants-aarch32.h b/src/aarch32/constants-aarch32.h
@@ -126,6 +126,10 @@ enum InstructionType {
   kAdds,
   kAddw,
   kAdr,
+  kAesd,
+  kAese,
+  kAesimc,
+  kAesmc,
   kAnd,
   kAnds,
   kAsr,
-Original file line number
+Diff line change
@@ Expand Up / @@ -126,6 +126,10 @@ enum InstructionType { @@
       kAdds,
       kAddw,
       kAdr,
+      kAesd,
+      kAese,
+      kAesimc,
+      kAesmc,
       kAnd,
       kAnds,
       kAsr,
@@ Expand Down @@