assembler-aarch64: Add support for emitting AES instructions

Adds support for emitting AESD, AESE, AESIMC, and AESMC
Linaro · Jan 26, 2022 · b0cd67c · b0cd67c
1 parent 0222be8
commit b0cd67c
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Showing 3 changed files with 35 additions and 1 deletion.
diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc
@@ -3862,6 +3862,24 @@ void Assembler::usdot(const VRegister& vd,
   Emit(VFormat(vd) | 0x0e809c00 | Rm(vm) | Rn(vn) | Rd(vd));
 }
 
+// clang-format off
+#define NEON_CRYPTO_AES_LIST(V) \
+  V(aesd,   NEON_AESD)          \
+  V(aese,   NEON_AESE)          \
+  V(aesmc,  NEON_AESMC)         \
+  V(aesimc, NEON_AESIMC)
+// clang-format on
+
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP)                         \
+  void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kAES));  \
+    VIXL_ASSERT(vd.Is16B() && vn.Is16B());                       \
+                                                                 \
+    Emit(VEC_OP | Rn(vn) | Rd(vd));                              \
+  }
+NEON_CRYPTO_AES_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
+
 void Assembler::faddp(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(CPUHas(CPUFeatures::kFP, CPUFeatures::kNEON));
   VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||

diff --git a/src/aarch64/assembler-aarch64.h b/src/aarch64/assembler-aarch64.h
@@ -3382,6 +3382,18 @@ class Assembler : public vixl::internal::AssemblerBase {
              const VRegister& vm,
              int vm_index);
 
+  // AES single round decryption
+  void aesd(const VRegister& vd, const VRegister& vn);
+
+  // AES single round encryption
+  void aese(const VRegister& vd, const VRegister& vn);
+
+  // AES mix columns
+  void aesmc(const VRegister& vd, const VRegister& vn);
+
+  // AES inverse mix columns
+  void aesimc(const VRegister& vd, const VRegister& vn);
+
   // Signed saturating rounding doubling multiply subtract returning high half
   // [Armv8.1].
   void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm);

diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h
@@ -1840,7 +1840,11 @@ enum Crypto3RegSHAOp {
 // Crypto - AES.
 enum CryptoAESOp {
   CryptoAESFixed = 0x4E280800,
-  CryptoAESFMask = 0xFF3E0C00
+  CryptoAESFMask = 0xFF3E0C00,
+  NEON_AESE      = CryptoAESFixed | 0x00004000,
+  NEON_AESD      = CryptoAESFixed | 0x00005000,
+  NEON_AESMC     = CryptoAESFixed | 0x00006000,
+  NEON_AESIMC    = CryptoAESFixed | 0x00007000
 };
 
 // NEON instructions with two register operands.