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ChibiOS: avoid bdshot fault on null event waiter #29379

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ChibiOS: avoid bdshot fault on null event waiter #29379

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0fb627f
HAL_ChibiOS: added code for finding null ptr write errors
tridge Feb 25, 2025
cb67ae5
HAL_ChibiOS: protect chEvtSignal from null waiter
tridge Feb 25, 2025
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5 changes: 3 additions & 2 deletions libraries/AP_HAL_ChibiOS/RCOutput.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1842,10 +1842,11 @@ __RAMFUNC__ void RCOutput::dma_unlock(virtual_timer_t* vt, void *p)
pwm_group *group = (pwm_group *)p;

group->dshot_state = DshotState::IDLE;
if (group->dshot_waiter != nullptr) {
auto *waiter = group->dshot_waiter;
if (waiter != nullptr) {
// tell the waiting process we've done the DMA. Note that
// dshot_waiter can be null if we have cancelled the send
chEvtSignalI(group->dshot_waiter, group->dshot_event_mask);
chEvtSignalI(waiter, group->dshot_event_mask);
}
chSysUnlockFromISR();
}
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12 changes: 9 additions & 3 deletions libraries/AP_HAL_ChibiOS/RCOutput_bdshot.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -515,8 +515,11 @@ __RAMFUNC__ void RCOutput::bdshot_finish_dshot_gcr_transaction(virtual_timer_t*
// although it should be possible to start the next DMAR transaction concurrently with receiving
// telemetry, in practice it seems to interfere with the DMA engine
if (group->shared_up_dma && group->bdshot.enabled) {
// next dshot pulse can go out now
chEvtSignalI(group->dshot_waiter, DSHOT_CASCADE);
auto *waiter = group->dshot_waiter;
if (waiter != nullptr) {
// next dshot pulse can go out now
chEvtSignalI(waiter, DSHOT_CASCADE);
}
}
#endif
// if using input capture DMA and sharing the UP and CH channels then clean up
Expand All @@ -541,7 +544,10 @@ __RAMFUNC__ void RCOutput::bdshot_finish_dshot_gcr_transaction(virtual_timer_t*
}

// tell the waiting process we've done the DMA
chEvtSignalI(group->dshot_waiter, group->dshot_event_mask);
auto *waiter = group->dshot_waiter;
if (waiter != nullptr) {
chEvtSignalI(waiter, group->dshot_event_mask);
}
#ifdef HAL_GPIO_LINE_GPIO56
TOGGLE_PIN_DEBUG(56);
#endif
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13 changes: 13 additions & 0 deletions libraries/AP_HAL_ChibiOS/Scheduler.cpp
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Expand Up @@ -623,6 +623,19 @@ void Scheduler::check_low_memory_is_zero()
}
#pragma GCC diagnostic pop
}

#if 0
/*
enable this on H7 to make writes to the first 1k of RAM on H7
produce a hard fault and crash dump
Comment on lines +629 to +630
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Suggested change
enable this on H7 to make writes to the first 1k of RAM on H7
produce a hard fault and crash dump
enable this on H7 to make writes to the first 1k of RAM on H7
produce a hard fault and crash dump instead of an internal error.
do not enable on production aircraft!

*/
mpuConfigureRegion(MPU_REGION_7,
0x0,
MPU_RASR_ATTR_AP_RO_RO |
MPU_RASR_SIZE_1K |
MPU_RASR_ENABLE);
mpuEnable(MPU_CTRL_PRIVDEFENA | MPU_CTRL_ENABLE);
#endif
}
#endif // STM32H7

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