Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

STM32N6: add CAN support #85554

Merged
merged 3 commits into from
Feb 13, 2025
+67 −0
Merged

STM32N6: add CAN support #85554

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
1187d51
dts: arm: st: n6: add fdcan
gautierg-st Jan 30, 2025
125e1e0
boards: st: stm32n6: enable fdcan for stm32n6 boards
gautierg-st Jan 30, 2025
597ec05
tests: drivers: can: add stm32n6 boards overlays
gautierg-st Jan 31, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions boards/st/nucleo_n657x0_q/doc/index.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,8 @@ The Zephyr ``nucleo_n657x0_q`` board supports the following hardware features:
+===========+============+=====================================+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| CAN/CANFD | on-chip | canbus |
+-----------+------------+-------------------------------------+
| DMA | on-chip | Direct Memory Access Controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
Expand Down Expand Up @@ -95,6 +97,8 @@ For more details please refer to `NUCLEO-N657X0-Q User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------

- FDCAN1_TX : PH2
- FDCAN1_RX : PD0
- LD1 : PO1
- LD2 : PG10
- USART_1_TX : PE5
Expand Down
9 changes: 9 additions & 0 deletions boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &axisram2;
zephyr,canbus = &fdcan1;
};

leds: leds {
Expand Down Expand Up @@ -110,6 +111,14 @@
apb5-prescaler = <1>;
};

&fdcan1 {
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
<&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
pinctrl-names = "default";
status = "okay";
};

&usart1 {
clocks = <&rcc STM32_CLOCK(APB2, 4)>,
<&rcc STM32_SRC_CKPER USART1_SEL(1)>;
Expand Down
1 change: 1 addition & 0 deletions boards/st/nucleo_n657x0_q/twister.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ ram: 1024
flash: 1024
supported:
- arduino_serial
- can
- dma
- gpio
- uart
Expand Down
4 changes: 4 additions & 0 deletions boards/st/stm32n6570_dk/doc/index.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,8 @@ The Zephyr ``stm32n6570_dk`` board supports the following hardware features:
+===========+============+=====================================+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| CAN/CANFD | on-chip | canbus |
+-----------+------------+-------------------------------------+
| DMA | on-chip | Direct Memory Access Controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
Expand Down Expand Up @@ -99,6 +101,8 @@ For more details please refer to `STM32N6570_DK User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------

- FDCAN1_TX : PH2
- FDCAN1_RX : PD0
- LD1 : PO1
- LD2 : PG10
- USART_1_TX : PE5
Expand Down
9 changes: 9 additions & 0 deletions boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &axisram2;
zephyr,canbus = &fdcan1;
};

aliases {
Expand Down Expand Up @@ -94,6 +95,14 @@
apb5-prescaler = <1>;
};

&fdcan1 {
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
<&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
pinctrl-names = "default";
status = "okay";
};

&usart1 {
clocks = <&rcc STM32_CLOCK(APB2, 4)>,
<&rcc STM32_SRC_CKPER USART1_SEL(1)>;
Expand Down
1 change: 1 addition & 0 deletions boards/st/stm32n6570_dk/twister.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ flash: 1024
vendor: st
supported:
- arduino_serial
- can
- dma
- gpio
- uart
Expand Down
33 changes: 33 additions & 0 deletions dts/arm/st/n6/stm32n6.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -362,6 +362,39 @@
};
};

fdcan1: can@5000a000 {
compatible = "st,stm32h7-fdcan";
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Perhaps it's time to come up with a new compatible for this integration of the Bosch M_CAN? If any of you have any insight in what to name this, I am all ears. The "h7" name was chosen since it was the first family (Zephyr-wise) where this integration was supported.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@henrikbrixandersen In Bosch M_CAN user manual on page 5: https://www.bosch-semiconductors.com/media/ip_modules/pdf_2/m_can/mcan_users_manual_v331.pdf register map is defined. Since a device follows this map "bosch,m-can" would be a good choise as you suggest.

reg = <0x5000A000 0x400>, <0x5000C000 0xd54>;
reg-names = "m_can", "message_ram";
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
interrupts = <180 0>, <181 0>, <186 0>;
interrupt-names = "int0", "int1", "calib";
bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
status = "disabled";
};

fdcan2: can@5000a400 {
compatible = "st,stm32h7-fdcan";
reg = <0x5000A400 0x400>, <0x5000C000 0x1aa8>;
reg-names = "m_can", "message_ram";
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
interrupts = <182 0>, <183 0>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0xd54 28 8 3 3 0 3 3>;
status = "disabled";
};

fdcan3: can@5000e800 {
compatible = "st,stm32h7-fdcan";
reg = <0x5000E800 0x400>, <0x5000C000 0x2800>;
reg-names = "m_can", "message_ram";
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
interrupts = <184 0>, <185 0>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x1aa8 28 8 3 3 0 3 3>;
status = "disabled";
};

usart1: serial@52001000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x52001000 0x400>;
Expand Down
1 change: 1 addition & 0 deletions tests/drivers/can/api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
CONFIG_TEST_USERSPACE=n
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Does this SoC not support userspace? Or is it just a matter of available MPU regions (if so, take a look at CONFIG_TEST_USERSPACE_WITHOUT_HW_STACK_PROTECTION)?

Either way, I think this would be better to set this from the board files instead of directly in each test for scalability. The CAN tests can't be the only ones affected by this limitation?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The problem lies with the MPU. On N6, the bootROM loads the application from external Flash into the RAM where it is executed. I suppose that, for userspace to work, the region in the RAM where the code lies should be configured as the Flash usually is, but I haven't looked at that for the moment.

I'll move CONFIG_TEST_USERSPACE=n in the board files.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Umm, in fact, I won't move the Kconfig to the board file. It gets overwritten by the prj.conf so the test fails...

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh. Right. 😞

1 change: 1 addition & 0 deletions tests/drivers/can/api/boards/stm32n6570_dk_stm32n657xx_sb.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
CONFIG_TEST_USERSPACE=n
2 changes: 2 additions & 0 deletions tests/drivers/can/timing/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
CONFIG_TEST_ALL_BITRATES=y
CONFIG_TEST_USERSPACE=n
2 changes: 2 additions & 0 deletions tests/drivers/can/timing/boards/stm32n6570_dk_stm32n657xx_sb.conf
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
CONFIG_TEST_ALL_BITRATES=y
CONFIG_TEST_USERSPACE=n
Loading