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Mediatek DSP fixups #844

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Dec 9, 2024
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Mediatek DSP fixups #844

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664c710
overlays/xtensa/mtk: Fixup and normalize file paths
andyross Nov 29, 2024
f13ee75
overlays/mtk: Add back Cadence-removed macro
andyross Nov 29, 2024
9eb7be0
overlays/mtk: Fix linker API
andyross Dec 1, 2024
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0 ...mtk_mt818x_adsp/binutils/xtensa-modules.c → ...mt818x_adsp/binutils/bfd/xtensa-modules.c
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4 changes: 4 additions & 0 deletions ..._mtk_mt818x_adsp/binutils/xtensa-config.h → ...18x_adsp/binutils/include/xtensa-config.h
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Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
4 changes: 4 additions & 0 deletions ...tensa_mtk_mt818x_adsp/gcc/xtensa-config.h → ...k_mt818x_adsp/gcc/include/xtensa-config.h
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Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
0 ...ensa_mtk_mt818x_adsp/gdb/xtensa-modules.c → ..._mtk_mt818x_adsp/gdb/bfd/xtensa-modules.c
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0 ...tensa_mtk_mt818x_adsp/gdb/xtensa-regmap.c → ...8x_adsp/gdb/gdb/gdbserver/xtensa-regmap.c
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0 ...tensa_mtk_mt818x_adsp/gdb/xtensa-xtregs.c → ...x_adsp/gdb/gdb/gdbserver/xtensa-xtregs.cc
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0 ...xtensa_mtk_mt818x_adsp/gdb/reg-xtensa.dat → ...8x_adsp/gdb/gdb/regformats/reg-xtensa.dat
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3 changes: 3 additions & 0 deletions ...tensa_mtk_mt818x_adsp/gdb/xtensa-config.c → ...a_mtk_mt818x_adsp/gdb/gdb/xtensa-config.c
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Expand Up @@ -23,6 +23,7 @@

#define XTENSA_CONFIG_VERSION 0x70

#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"

Expand Down Expand Up @@ -554,7 +555,9 @@ xtensa_register_t rmap[] =
XTREG_END
};

extern xtensa_register_t xtensa_rmap[] __attribute__((alias("rmap")));

xtensa_gdbarch_tdep xtensa_tdep (rmap);

#ifdef XTENSA_CONFIG_INSTANTIATE
XTENSA_CONFIG_INSTANTIATE(rmap,16)
Expand Down
0 ...tensa_mtk_mt8196_adsp/gdb/xtensa-xtregs.c → ...a_mtk_mt818x_adsp/gdb/gdb/xtensa-xtregs.c
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4 changes: 4 additions & 0 deletions ...tensa_mtk_mt818x_adsp/gdb/xtensa-config.h → ...k_mt818x_adsp/gdb/include/xtensa-config.h
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Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
0 ..._mtk_mt818x_adsp/xtensa/config/core-isa.h → ...s/xtensa/include/xtensa/config/core-isa.h
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0 ...95_adsp/gdb/gdb/gdbserver/xtensa-xtregs.c → ...5_adsp/gdb/gdb/gdbserver/xtensa-xtregs.cc
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4 changes: 3 additions & 1 deletion overlays/xtensa_mtk_mt8195_adsp/gdb/gdb/xtensa-config.c
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Expand Up @@ -113,7 +113,7 @@ const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };


/* Register map. */
static xtensa_register_t rmap[] =
xtensa_register_t rmap[] =
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oof. global with such a generic name doesn't seem ideal. I assume this is required for ABI though?

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Yeah, these overlays get dropped on top of the binutils source code (that starts out populated with an old Xtensa "sample_controller" file). It's... not super clean. FWIW the Espressif-contributed work on LLVM is capable of generating a single toolchain where all these deltas are captured by a config struct instead. It appears to build Zephyr last I checked, though I haven't had time to see what would be needed to turn it into a "Lite Xtensa SDK".

(Worth nothing that there is no lldb work there that I've seen, so we'd still need to build binutils and gdb I guess. Though there might be some savings)

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FWIW the Espressif-contributed work on LLVM is capable of generating a single toolchain where all these deltas are captured by a config struct instead. It appears to build Zephyr last I checked, though I haven't had time to see what would be needed to turn it into a "Lite Xtensa SDK".

Interesting. Since LLVM will be part of Zephyr SDK from 0.18.0, we can potentially explore this option. At least, we can drop the GCC builds for the Xtensa toolchain variants whose users do not explicitly require GCC (well, if LLVM works, why should they?)

{
/* idx ofs bi sz al targno flags cp typ group name */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
Expand Down Expand Up @@ -496,4 +496,6 @@ static xtensa_register_t rmap[] =
XTREG_END
};

extern xtensa_register_t xtensa_rmap[] __attribute__((alias("rmap")));
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^


xtensa_gdbarch_tdep xtensa_tdep (rmap);
0 ...mtk_mt8196_adsp/binutils/xtensa-modules.c → ...mt8196_adsp/binutils/bfd/xtensa-modules.c
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4 changes: 4 additions & 0 deletions ...tensa_mtk_mt8196_adsp/gcc/xtensa-config.h → ...196_adsp/binutils/include/xtensa-config.h
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Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
4 changes: 4 additions & 0 deletions ...tensa_mtk_mt8196_adsp/gdb/xtensa-config.h → ...k_mt8196_adsp/gcc/include/xtensa-config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
0 ...ensa_mtk_mt8196_adsp/gdb/xtensa-modules.c → ..._mtk_mt8196_adsp/gdb/bfd/xtensa-modules.c
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0 ...tensa_mtk_mt8196_adsp/gdb/xtensa-regmap.c → ...96_adsp/gdb/gdb/gdbserver/xtensa-regmap.c
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95 changes: 95 additions & 0 deletions overlays/xtensa_mtk_mt8196_adsp/gdb/gdb/gdbserver/xtensa-xtregs.cc
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@@ -0,0 +1,95 @@
/* Customized table mapping between kernel xtregset and GDB register cache.

Copyright (c) 2007-2010 Tensilica Inc.

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */


typedef struct {
int gdb_regnum;
int gdb_offset;
int ptrace_cp_offset;
int ptrace_offset;
int size;
int coproc;
int dbnum;
char* name
;} xtensa_regtable_t;

#define XTENSA_ELF_XTREG_SIZE 404

const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
{ 76, 304, 0, 0, 4, -1, 0x0204, "br" },
{ 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" },
{ 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" },
{ 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
{ 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" },
{ 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" },
{ 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" },
{ 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" },
{ 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" },
{ 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" },
{ 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" },
{ 88, 352, 128, 144, 8, 1, 0x1000, "aed0" },
{ 89, 360, 136, 152, 8, 1, 0x1001, "aed1" },
{ 90, 368, 144, 160, 8, 1, 0x1002, "aed2" },
{ 91, 376, 152, 168, 8, 1, 0x1003, "aed3" },
{ 92, 384, 160, 176, 8, 1, 0x1004, "aed4" },
{ 93, 392, 168, 184, 8, 1, 0x1005, "aed5" },
{ 94, 400, 176, 192, 8, 1, 0x1006, "aed6" },
{ 95, 408, 184, 200, 8, 1, 0x1007, "aed7" },
{ 96, 416, 192, 208, 8, 1, 0x1008, "aed8" },
{ 97, 424, 200, 216, 8, 1, 0x1009, "aed9" },
{ 98, 432, 208, 224, 8, 1, 0x100a, "aed10" },
{ 99, 440, 216, 232, 8, 1, 0x100b, "aed11" },
{ 100, 448, 224, 240, 8, 1, 0x100c, "aed12" },
{ 101, 456, 232, 248, 8, 1, 0x100d, "aed13" },
{ 102, 464, 240, 256, 8, 1, 0x100e, "aed14" },
{ 103, 472, 248, 264, 8, 1, 0x100f, "aed15" },
{ 104, 480, 256, 272, 8, 1, 0x1010, "aed16" },
{ 105, 488, 264, 280, 8, 1, 0x1011, "aed17" },
{ 106, 496, 272, 288, 8, 1, 0x1012, "aed18" },
{ 107, 504, 280, 296, 8, 1, 0x1013, "aed19" },
{ 108, 512, 288, 304, 8, 1, 0x1014, "aed20" },
{ 109, 520, 296, 312, 8, 1, 0x1015, "aed21" },
{ 110, 528, 304, 320, 8, 1, 0x1016, "aed22" },
{ 111, 536, 312, 328, 8, 1, 0x1017, "aed23" },
{ 112, 544, 320, 336, 8, 1, 0x1018, "aed24" },
{ 113, 552, 328, 344, 8, 1, 0x1019, "aed25" },
{ 114, 560, 336, 352, 8, 1, 0x101a, "aed26" },
{ 115, 568, 344, 360, 8, 1, 0x101b, "aed27" },
{ 116, 576, 352, 368, 8, 1, 0x101c, "aed28" },
{ 117, 584, 360, 376, 8, 1, 0x101d, "aed29" },
{ 118, 592, 368, 384, 8, 1, 0x101e, "aed30" },
{ 119, 600, 376, 392, 8, 1, 0x101f, "aed31" },
{ 120, 608, 64, 80, 16, 1, 0x1020, "u0" },
{ 121, 624, 80, 96, 16, 1, 0x1021, "u1" },
{ 122, 640, 96, 112, 16, 1, 0x1022, "u2" },
{ 123, 656, 112, 128, 16, 1, 0x1023, "u3" },
{ 124, 672, 384, 400, 1, 1, 0x1024, "aep0" },
{ 125, 673, 385, 401, 1, 1, 0x1025, "aep1" },
{ 126, 674, 386, 402, 1, 1, 0x1026, "aep2" },
{ 127, 675, 387, 403, 1, 1, 0x1027, "aep3" },
{ 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" },
{ 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" },
{ 0 }
};

0 ...xtensa_mtk_mt8196_adsp/gdb/reg-xtensa.dat → ...96_adsp/gdb/gdb/regformats/reg-xtensa.dat
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3 changes: 3 additions & 0 deletions ...tensa_mtk_mt8196_adsp/gdb/xtensa-config.c → ...a_mtk_mt8196_adsp/gdb/gdb/xtensa-config.c
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Expand Up @@ -23,6 +23,7 @@

#define XTENSA_CONFIG_VERSION 0x70

#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"

Expand Down Expand Up @@ -554,7 +555,9 @@ xtensa_register_t rmap[] =
XTREG_END
};

extern xtensa_register_t xtensa_rmap[] __attribute__((alias("rmap")));

xtensa_gdbarch_tdep xtensa_tdep (rmap);

#ifdef XTENSA_CONFIG_INSTANTIATE
XTENSA_CONFIG_INSTANTIATE(rmap,16)
Expand Down
95 changes: 95 additions & 0 deletions overlays/xtensa_mtk_mt8196_adsp/gdb/gdb/xtensa-xtregs.c
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@@ -0,0 +1,95 @@
/* Customized table mapping between kernel xtregset and GDB register cache.

Copyright (c) 2007-2010 Tensilica Inc.

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */


typedef struct {
int gdb_regnum;
int gdb_offset;
int ptrace_cp_offset;
int ptrace_offset;
int size;
int coproc;
int dbnum;
char* name
;} xtensa_regtable_t;

#define XTENSA_ELF_XTREG_SIZE 404

const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
{ 76, 304, 0, 0, 4, -1, 0x0204, "br" },
{ 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" },
{ 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" },
{ 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
{ 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" },
{ 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" },
{ 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" },
{ 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" },
{ 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" },
{ 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" },
{ 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" },
{ 88, 352, 128, 144, 8, 1, 0x1000, "aed0" },
{ 89, 360, 136, 152, 8, 1, 0x1001, "aed1" },
{ 90, 368, 144, 160, 8, 1, 0x1002, "aed2" },
{ 91, 376, 152, 168, 8, 1, 0x1003, "aed3" },
{ 92, 384, 160, 176, 8, 1, 0x1004, "aed4" },
{ 93, 392, 168, 184, 8, 1, 0x1005, "aed5" },
{ 94, 400, 176, 192, 8, 1, 0x1006, "aed6" },
{ 95, 408, 184, 200, 8, 1, 0x1007, "aed7" },
{ 96, 416, 192, 208, 8, 1, 0x1008, "aed8" },
{ 97, 424, 200, 216, 8, 1, 0x1009, "aed9" },
{ 98, 432, 208, 224, 8, 1, 0x100a, "aed10" },
{ 99, 440, 216, 232, 8, 1, 0x100b, "aed11" },
{ 100, 448, 224, 240, 8, 1, 0x100c, "aed12" },
{ 101, 456, 232, 248, 8, 1, 0x100d, "aed13" },
{ 102, 464, 240, 256, 8, 1, 0x100e, "aed14" },
{ 103, 472, 248, 264, 8, 1, 0x100f, "aed15" },
{ 104, 480, 256, 272, 8, 1, 0x1010, "aed16" },
{ 105, 488, 264, 280, 8, 1, 0x1011, "aed17" },
{ 106, 496, 272, 288, 8, 1, 0x1012, "aed18" },
{ 107, 504, 280, 296, 8, 1, 0x1013, "aed19" },
{ 108, 512, 288, 304, 8, 1, 0x1014, "aed20" },
{ 109, 520, 296, 312, 8, 1, 0x1015, "aed21" },
{ 110, 528, 304, 320, 8, 1, 0x1016, "aed22" },
{ 111, 536, 312, 328, 8, 1, 0x1017, "aed23" },
{ 112, 544, 320, 336, 8, 1, 0x1018, "aed24" },
{ 113, 552, 328, 344, 8, 1, 0x1019, "aed25" },
{ 114, 560, 336, 352, 8, 1, 0x101a, "aed26" },
{ 115, 568, 344, 360, 8, 1, 0x101b, "aed27" },
{ 116, 576, 352, 368, 8, 1, 0x101c, "aed28" },
{ 117, 584, 360, 376, 8, 1, 0x101d, "aed29" },
{ 118, 592, 368, 384, 8, 1, 0x101e, "aed30" },
{ 119, 600, 376, 392, 8, 1, 0x101f, "aed31" },
{ 120, 608, 64, 80, 16, 1, 0x1020, "u0" },
{ 121, 624, 80, 96, 16, 1, 0x1021, "u1" },
{ 122, 640, 96, 112, 16, 1, 0x1022, "u2" },
{ 123, 656, 112, 128, 16, 1, 0x1023, "u3" },
{ 124, 672, 384, 400, 1, 1, 0x1024, "aep0" },
{ 125, 673, 385, 401, 1, 1, 0x1025, "aep1" },
{ 126, 674, 386, 402, 1, 1, 0x1026, "aep2" },
{ 127, 675, 387, 403, 1, 1, 0x1027, "aep3" },
{ 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" },
{ 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" },
{ 0 }
};

4 changes: 4 additions & 0 deletions ..._mtk_mt8196_adsp/binutils/xtensa-config.h → ...k_mt8196_adsp/gdb/include/xtensa-config.h
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Expand Up @@ -183,3 +183,7 @@


#endif /* !XTENSA_CONFIG_H */

#ifndef XCHAL_HAVE_PREDICTED_BRANCHES
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* Needed by Zephyr SDK binutils */
#endif
0 ..._mtk_mt8196_adsp/xtensa/config/core-isa.h → ...s/xtensa/include/xtensa/config/core-isa.h
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