s32: soc: s32z2: update PSI5 clock sources

Update the PSI5 clock sources to support bitrates of 125 kbps and 189 kbps, corresponding to 4 MHz and 6 MHz, respectively. Signed-off-by: Cong Nguyen Huu <[email protected]>
zephyrproject-rtos · Jan 6, 2025 · 4961db3 · 4961db3
1 parent 7f8d816
commit 4961db3
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/s32/soc/s32z270/src/Clock_Ip_Cfg.c b/s32/soc/s32z270/src/Clock_Ip_Cfg.c
@@ -945,9 +945,9 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I
     #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 23U
     {
         P0_PSI5_189K_CLK,                    /* name */
-        3306U,                              /* value */
+        8U,                              /* value */
         {
-            2U,
+            0U,
         }
     },
     #endif
@@ -1215,9 +1215,9 @@ static const Clock_Ip_DividerConfigType Clock_Ip_DividerConfigurations_0[CLOCK_I
     #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 50U
     {
         P4_PSI5_189K_CLK,                    /* name */
-        3306U,                              /* value */
+        8U,                              /* value */
         {
-            2U,
+            0U,
         }
     },
     #endif