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Unused CLK has been deleted, increased frequency for the screen and mic #189

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merged 2 commits into from
Nov 11, 2024
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Unused CLK has been deleted, increased frequency for the screen and mic #189

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ae240c7
Unused CLK has been deleted, increased frequency for the screen and m…
oVadim Nov 10, 2024
d8cafb5
Fixed small error
oVadim Nov 10, 2024
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4 changes: 0 additions & 4 deletions boards/tang_nano_20k_lcd_480_272_tm1638/board_specific_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -354,10 +354,6 @@ module board_specific_top
`endif
i_lcd
(
`ifdef USE_LCD_800_480
.CLK ( lcd_module_clk ),
`endif

.PixelClk ( LCD_CLK ),
.nRST ( ~ rst ),

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2 changes: 0 additions & 2 deletions boards/tang_nano_20k_lcd_800_480_tm1638/board_specific_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -292,8 +292,6 @@ module board_specific_top

lcd_800_480 i_lcd
(
.CLK ( lcd_module_clk ),

.PixelClk ( LCD_CLK ),
.nRST ( ~ rst ),

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10 changes: 5 additions & 5 deletions boards/tang_nano_20k_lcd_800_480_tm1638/gowin_rpll.ipc
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Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,14 @@ CLKFB_SOURCE=0
CLKIN_FREQ=27
CLKOUTD=true
CLKOUTD_BYPASS=false
CLKOUTD_FREQ=33.33
CLKOUTD_SOURCE_CLKOUT=true
CLKOUTD_TOLERANCE=1
CLKOUTP=false
CLKOUTD_FREQ=48.937
CLKOUT_BYPASS=false
CLKOUTD_SOURCE_CLKOUT=true
CLKOUT_DIVIDE_DYN=true
CLKOUT_FREQ=200
CLKOUT_TOLERANCE=1
CLKOUTD_TOLERANCE=1
CLKOUT_FREQ=391.5
CLKOUT_TOLERANCE=0
DYNAMIC=true
LANG=0
LOCK_EN=false
Expand Down
14 changes: 7 additions & 7 deletions boards/tang_nano_20k_lcd_800_480_tm1638/gowin_rpll.v
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//GOWIN Version: V1.9.9 Beta-4 Education
//Tool Version: V1.9.10.02
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sat Sep 14 10:35:05 2024
//Created Time: Sun Nov 10 02:51:25 2024

module Gowin_rPLL (clkout, clkoutd, clkin);

Expand Down Expand Up @@ -40,11 +40,11 @@ rPLL rpll_inst (

defparam rpll_inst.FCLKIN = "27";
defparam rpll_inst.DYN_IDIV_SEL = "false";
defparam rpll_inst.IDIV_SEL = 4;
defparam rpll_inst.IDIV_SEL = 0;
defparam rpll_inst.DYN_FBDIV_SEL = "false";
defparam rpll_inst.FBDIV_SEL = 36;
defparam rpll_inst.FBDIV_SEL = 2;
defparam rpll_inst.DYN_ODIV_SEL = "false";
defparam rpll_inst.ODIV_SEL = 4;
defparam rpll_inst.ODIV_SEL = 8;
defparam rpll_inst.PSDA_SEL = "0000";
defparam rpll_inst.DYN_DA_EN = "true";
defparam rpll_inst.DUTYDA_SEL = "1000";
Expand All @@ -56,7 +56,7 @@ defparam rpll_inst.CLKFB_SEL = "internal";
defparam rpll_inst.CLKOUT_BYPASS = "false";
defparam rpll_inst.CLKOUTP_BYPASS = "false";
defparam rpll_inst.CLKOUTD_BYPASS = "false";
defparam rpll_inst.DYN_SDIV_SEL = 6;
defparam rpll_inst.DYN_SDIV_SEL = 2;
defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
defparam rpll_inst.DEVICE = "GW2A-18C";
Expand Down
4 changes: 0 additions & 4 deletions boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -349,10 +349,6 @@ module board_specific_top
`endif
i_lcd
(
`ifdef USE_LCD_800_480
.CLK ( lcd_module_clk ),
`endif

.PixelClk ( LARGE_LCD_CK ),
.nRST ( ~ rst ),

Expand Down
10 changes: 5 additions & 5 deletions boards/tang_primer_20k_dock_lcd_800_480_no_tm1638/gowin_rpll.ipc
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Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,14 @@ CLKFB_SOURCE=0
CLKIN_FREQ=27
CLKOUTD=true
CLKOUTD_BYPASS=false
CLKOUTD_FREQ=33.33
CLKOUTD_SOURCE_CLKOUT=true
CLKOUTD_TOLERANCE=1
CLKOUTP=false
CLKOUTD_FREQ=48.937
CLKOUT_BYPASS=false
CLKOUTD_SOURCE_CLKOUT=true
CLKOUT_DIVIDE_DYN=true
CLKOUT_FREQ=200
CLKOUT_TOLERANCE=1
CLKOUTD_TOLERANCE=1
CLKOUT_FREQ=391.5
CLKOUT_TOLERANCE=0
DYNAMIC=true
LANG=0
LOCK_EN=false
Expand Down
12 changes: 6 additions & 6 deletions boards/tang_primer_20k_dock_lcd_800_480_no_tm1638/gowin_rpll.v
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.9.03 Education (64-bit)
//Tool Version: V1.9.10.02
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Fri Oct 11 10:54:06 2024
//Created Time: Sun Nov 10 02:51:25 2024

module Gowin_rPLL (clkout, clkoutd, clkin);

Expand Down Expand Up @@ -40,11 +40,11 @@ rPLL rpll_inst (

defparam rpll_inst.FCLKIN = "27";
defparam rpll_inst.DYN_IDIV_SEL = "false";
defparam rpll_inst.IDIV_SEL = 4;
defparam rpll_inst.IDIV_SEL = 0;
defparam rpll_inst.DYN_FBDIV_SEL = "false";
defparam rpll_inst.FBDIV_SEL = 36;
defparam rpll_inst.FBDIV_SEL = 2;
defparam rpll_inst.DYN_ODIV_SEL = "false";
defparam rpll_inst.ODIV_SEL = 4;
defparam rpll_inst.ODIV_SEL = 8;
defparam rpll_inst.PSDA_SEL = "0000";
defparam rpll_inst.DYN_DA_EN = "true";
defparam rpll_inst.DUTYDA_SEL = "1000";
Expand All @@ -56,7 +56,7 @@ defparam rpll_inst.CLKFB_SEL = "internal";
defparam rpll_inst.CLKOUT_BYPASS = "false";
defparam rpll_inst.CLKOUTP_BYPASS = "false";
defparam rpll_inst.CLKOUTD_BYPASS = "false";
defparam rpll_inst.DYN_SDIV_SEL = 6;
defparam rpll_inst.DYN_SDIV_SEL = 2;
defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
defparam rpll_inst.DEVICE = "GW2A-18C";
Expand Down
11 changes: 5 additions & 6 deletions boards/tang_primer_20k_dock_lcd_800_480_tm1638/board_specific_top.sv
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Expand Up @@ -68,6 +68,7 @@ module board_specific_top
);

wire clk = CLK;
wire mic_clk = LCD_CLK;

//------------------------------------------------------------------------

Expand Down Expand Up @@ -262,15 +263,13 @@ module board_specific_top

Gowin_rPLL i_Gowin_rPLL
(
.clkout ( lcd_module_clk ), // 200 MHz
.clkoutd ( LCD_CLK ), // 33.33 MHz
.clkin ( clk ) // 27 MHz
.clkout ( lcd_module_clk ), // 391.5 MHz
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Это нужно обсудить. Зачем тут 48 MHz и тем более 391? В примерах от говина такого нет TangNano-20K-example/rgb_lcd/lcd_800_400/color_bar/src/gowin_rpll/gowin_rpll.ipc

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Проверил на 5' LCD, на 49 мгц работает хорошо. Эту частоту можно использовать там, где у других плат 50 мгц. 391 мгц (она пока не используется) - я хотел получить стандартную частоту для звука 48 кгц, чтоб можно было записывать, передавать и воспроизводить готовые файлы (391/64 /6/2 /64). Для существующих лаб это пока неактуально. У HDMI потом можно сделать 391/2 и 391/2 /5 двумя делителями. И сделать одновременный вывод на HDMI и LCD.

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@yuri-panchul yuri-panchul Nov 11, 2024 •
edited
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Проблема тут вот в чем. При приеме данных из микрофона в модуль lab_top может возникнуть метастабильное состояние (из домена 50 MHz в домен 27 MHz). Можно конечно и главный дизайн сделать на такой частоте 50 MHz - тогда проблема метастабильного состояния снимается. И вообще сделать все платы у которых 27 MHz clock - с clock на 50 MHz (правда потом непонятно не вылезет ли у нас negative slack где-нибудь).

См. http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

Что касается HDMI так оно уже работает с IP от производителя.

Но если вы хотите экспериментировать в рамках одной платы 20k, то я в принципе не против, пока оно все работает.

Насчет CLK - так как оно стояло в модуле от производителя, я его просто закомментарю там, так как я хочу сохранить исходный модуль от производителя с минимумом изменений, даже если он неоптимален, пока не появится серьезной причины его переписать.

.clkoutd ( LCD_CLK ), // 48.937 MHz
.clkin ( clk ) // 27 MHz
);

lcd_800_480 i_lcd
(
.CLK ( lcd_module_clk ),

.PixelClk ( LCD_CLK ),
.nRST ( ~ rst ),

Expand All @@ -297,7 +296,7 @@ module board_specific_top
)
i_microphone
(
.clk ( clk ),
.clk ( mic_clk ),
.rst ( rst ),
.lr ( GPIO_1 [1] ),
.ws ( GPIO_1 [2] ),
Expand Down
10 changes: 5 additions & 5 deletions boards/tang_primer_20k_dock_lcd_800_480_tm1638/gowin_rpll.ipc
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Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,14 @@ CLKFB_SOURCE=0
CLKIN_FREQ=27
CLKOUTD=true
CLKOUTD_BYPASS=false
CLKOUTD_FREQ=33.33
CLKOUTD_SOURCE_CLKOUT=true
CLKOUTD_TOLERANCE=1
CLKOUTP=false
CLKOUTD_FREQ=48.937
CLKOUT_BYPASS=false
CLKOUTD_SOURCE_CLKOUT=true
CLKOUT_DIVIDE_DYN=true
CLKOUT_FREQ=200
CLKOUT_TOLERANCE=1
CLKOUTD_TOLERANCE=1
CLKOUT_FREQ=391.5
CLKOUT_TOLERANCE=0
DYNAMIC=true
LANG=0
LOCK_EN=false
Expand Down
12 changes: 6 additions & 6 deletions boards/tang_primer_20k_dock_lcd_800_480_tm1638/gowin_rpll.v
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.9.03 Education (64-bit)
//Tool Version: V1.9.10.02
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Fri Oct 11 10:54:06 2024
//Created Time: Sun Nov 10 02:51:25 2024

module Gowin_rPLL (clkout, clkoutd, clkin);

Expand Down Expand Up @@ -40,11 +40,11 @@ rPLL rpll_inst (

defparam rpll_inst.FCLKIN = "27";
defparam rpll_inst.DYN_IDIV_SEL = "false";
defparam rpll_inst.IDIV_SEL = 4;
defparam rpll_inst.IDIV_SEL = 0;
defparam rpll_inst.DYN_FBDIV_SEL = "false";
defparam rpll_inst.FBDIV_SEL = 36;
defparam rpll_inst.FBDIV_SEL = 2;
defparam rpll_inst.DYN_ODIV_SEL = "false";
defparam rpll_inst.ODIV_SEL = 4;
defparam rpll_inst.ODIV_SEL = 8;
defparam rpll_inst.PSDA_SEL = "0000";
defparam rpll_inst.DYN_DA_EN = "true";
defparam rpll_inst.DUTYDA_SEL = "1000";
Expand All @@ -56,7 +56,7 @@ defparam rpll_inst.CLKFB_SEL = "internal";
defparam rpll_inst.CLKOUT_BYPASS = "false";
defparam rpll_inst.CLKOUTP_BYPASS = "false";
defparam rpll_inst.CLKOUTD_BYPASS = "false";
defparam rpll_inst.DYN_SDIV_SEL = 6;
defparam rpll_inst.DYN_SDIV_SEL = 2;
defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
defparam rpll_inst.DEVICE = "GW2A-18C";
Expand Down
1 change: 0 additions & 1 deletion peripherals/lcd_800_480.sv
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Expand Up @@ -2,7 +2,6 @@

module lcd_800_480
(
input CLK,
input nRST,

input PixelClk,
Expand Down