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Update project_process_config_01.json and project_process_config_02.json
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73 changes: 42 additions & 31 deletions
73
boards/tang_nano_20k_lcd_480_272_tm1638/project_process_config_01.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,32 +1,43 @@ | ||
| { | ||
| "Allow_Duplicate_Modules" : false, | ||
| "Annotated_Properties_for_Analyst" : true, | ||
| "BACKGROUND_PROGRAMMING" : "off", | ||
| "COMPRESS" : false, | ||
| "CRC_CHECK" : true, | ||
| "Clock_Conversion" : true, | ||
| "Clock_Route_Order" : 0, | ||
| "Correct_Hold_Violation" : true, | ||
| "DONE" : true, | ||
| "DOWNLOAD_SPEED" : "default", | ||
| "Default_Enum_Encoding" : "default", | ||
| "Disable_Insert_Pad" : false, | ||
| "ENCRYPTION_KEY" : false, | ||
| "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", | ||
| "FORMAT" : "binary", | ||
| "FSM Compiler" : true, | ||
| "Fanout_Guide" : 10000, | ||
| "Frequency" : "Auto", | ||
| "Generate_Constraint_File_of_Ports" : false, | ||
| "Generate_IBIS_File" : false, | ||
| "Generate_Plain_Text_Timing_Report" : false, | ||
| "Generate_Post_PNR_Simulation_Model_File" : false, | ||
| "Generate_Post_Place_File" : false, | ||
| "Generate_SDF_File" : false, | ||
| "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, | ||
| "GwSyn_Loop_Limit" : 2000, | ||
| "HOTBOOT" : false, | ||
| "I2C" : false, | ||
| "I2C_SLAVE_ADDR" : "00", | ||
| "Implicit_Initial_Value_Support" : false, | ||
| "IncludePath" : [ | ||
| "Allow_Duplicate_Modules" : false, | ||
| "Annotated_Properties_for_Analyst" : true, | ||
| "BACKGROUND_PROGRAMMING" : "off", | ||
| "CMSER" : false, | ||
| "CMSER_CHECKSUM" : false, | ||
| "CMSER_MODE" : "auto", | ||
| "COMPRESS" : false, | ||
| "CPU" : false, | ||
| "CRC_CHECK" : true, | ||
| "Clock_Conversion" : true, | ||
| "Clock_Route_Order" : 0, | ||
| "Correct_Hold_Violation" : true, | ||
| "DONE" : false, | ||
| "DOWNLOAD_SPEED" : "default", | ||
| "Default_Enum_Encoding" : "default", | ||
| "Disable_Insert_Pad" : false, | ||
| "ENABLE_MERGE_MODE" : false, | ||
| "ENCRYPTION_KEY" : false, | ||
| "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", | ||
| "ERROR_DECTION_AND_CORRECTION" : false, | ||
| "ERROR_DECTION_ONLY" : false, | ||
| "ERROR_INJECTION" : false, | ||
| "EXTERNAL_MASTER_CONFIG_CLOCK" : false, | ||
| "FORMAT" : "txt", | ||
| "FREQUENCY_DIVIDER" : "", | ||
| "FSM Compiler" : true, | ||
| "Fanout_Guide" : 10000, | ||
| "Frequency" : "Auto", | ||
| "Generate_Constraint_File_of_Ports" : false, | ||
| "Generate_IBIS_File" : false, | ||
| "Generate_Plain_Text_Timing_Report" : false, | ||
| "Generate_Post_PNR_Simulation_Model_File" : false, | ||
| "Generate_Post_Place_File" : false, | ||
| "Generate_SDF_File" : false, | ||
| "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, | ||
| "GwSyn_Loop_Limit" : 2000, | ||
| "HOTBOOT" : false, | ||
| "I2C" : false, | ||
| "I2C_SLAVE_ADDR" : "00", | ||
| "Implicit_Initial_Value_Support" : false, | ||
| "IncludePath" : [ | ||
|
|
115 changes: 62 additions & 53 deletions
115
boards/tang_nano_20k_lcd_480_272_tm1638/project_process_config_02.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,53 +1,62 @@ | ||
| ], | ||
| "Incremental_Compile" : "", | ||
| "Initialize_Primitives" : false, | ||
| "JTAG" : false, | ||
| "MODE_IO" : false, | ||
| "MSPI" : false, | ||
| "Multiple_File_Compilation_Unit" : true, | ||
| "Number_of_Critical_Paths" : "", | ||
| "Number_of_Start/End_Points" : "", | ||
| "OUTPUT_BASE_NAME" : "fpga_project", | ||
| "POWER_ON_RESET_MONITOR" : true, | ||
| "PRINT_BSRAM_VALUE" : true, | ||
| "PROGRAM_DONE_BYPASS" : false, | ||
| "Pipelining" : true, | ||
| "PlaceInRegToIob" : true, | ||
| "PlaceIoRegToIob" : true, | ||
| "PlaceOutRegToIob" : true, | ||
| "Place_Option" : "0", | ||
| "Process_Configuration_Verion" : "1.0", | ||
| "Promote_Physical_Constraint_Warning_to_Error" : true, | ||
| "Push_Tristates" : true, | ||
| "READY" : true, | ||
| "RECONFIG_N" : false, | ||
| "Ram_RW_Check" : true, | ||
| "Report_Auto-Placed_Io_Information" : false, | ||
| "Resolve_Mixed_Drivers" : false, | ||
| "Resource_Sharing" : true, | ||
| "Retiming" : false, | ||
| "Route_Maxfan" : 23, | ||
| "Route_Option" : "0", | ||
| "Run_Timing_Driven" : true, | ||
| "SECURE_MODE" : false, | ||
| "SECURITY_BIT" : true, | ||
| "SPI_FLASH_ADDR" : "00000000", | ||
| "SSPI" : true, | ||
| "Show_All_Warnings" : false, | ||
| "Synthesis On/Off Implemented as Translate On/Off" : false, | ||
| "Synthesize_tool" : "GowinSyn", | ||
| "TclPre" : "", | ||
| "TopModule" : "board_specific_top", | ||
| "USERCODE" : "default", | ||
| "Unused_Pin" : "As_input_tri_stated_with_pull_up", | ||
| "Update_Compile_Point_Timing_Data" : false, | ||
| "Use_Clock_Period_for_Unconstrainted IO" : false, | ||
| "VCCAUX" : 3.3, | ||
| "VHDL_Standard" : "VHDL_Std_1993", | ||
| "Verilog_Standard" : "Vlg_Std_Sysv2017", | ||
| "WAKE_UP" : "0", | ||
| "Write_Vendor_Constraint_File" : true, | ||
| "dsp_balance" : false, | ||
| "show_all_warnings" : false, | ||
| "turn_off_bg" : false | ||
| } | ||
| ], | ||
| "Incremental_Compile" : "", | ||
| "Initialize_Primitives" : false, | ||
| "JTAG" : false, | ||
| "MODE_IO" : false, | ||
| "MSPI" : true, | ||
| "MSPI_JUMP" : false, | ||
| "MULTIBOOT_ADDRESS_WIDTH" : "24", | ||
| "MULTIBOOT_MODE" : "Normal", | ||
| "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", | ||
| "MULTIJUMP_ADDRESS_WIDTH" : "24", | ||
| "MULTIJUMP_MODE" : "Normal", | ||
| "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", | ||
| "Multi_Boot" : true, | ||
| "Multiple_File_Compilation_Unit" : true, | ||
| "Number_of_Critical_Paths" : "", | ||
| "Number_of_Start/End_Points" : "", | ||
| "OSC_DIVIDER" : "8", | ||
| "OUTPUT_BASE_NAME" : "Tang_nano_20K_LCD", | ||
| "POWER_ON_RESET_MONITOR" : true, | ||
| "PRINT_BSRAM_VALUE" : true, | ||
| "PROGRAM_DONE_BYPASS" : false, | ||
| "Pipelining" : true, | ||
| "PlaceInRegToIob" : true, | ||
| "PlaceIoRegToIob" : true, | ||
| "PlaceOutRegToIob" : true, | ||
| "Place_Option" : "0", | ||
| "Process_Configuration_Verion" : "1.0", | ||
| "Promote_Physical_Constraint_Warning_to_Error" : false, | ||
| "Push_Tristates" : true, | ||
| "READY" : false, | ||
| "RECONFIG_N" : false, | ||
| "Ram_RW_Check" : true, | ||
| "Report_Auto-Placed_Io_Information" : false, | ||
| "Resolve_Mixed_Drivers" : false, | ||
| "Resource_Sharing" : true, | ||
| "Retiming" : false, | ||
| "Route_Maxfan" : 23, | ||
| "Route_Option" : "0", | ||
| "Run_Timing_Driven" : true, | ||
| "SECURE_MODE" : false, | ||
| "SECURITY_BIT" : true, | ||
| "SSPI" : true, | ||
| "STOP_CMSER" : false, | ||
| "Show_All_Warnings" : false, | ||
| "Synthesis On/Off Implemented as Translate On/Off" : false, | ||
| "Synthesize_tool" : "GowinSyn", | ||
| "TclPre" : "", | ||
| "TopModule" : "TOP", | ||
| "USERCODE" : "default", | ||
| "Unused_Pin" : "As_input_tri_stated_with_pull_up", | ||
| "Update_Compile_Point_Timing_Data" : false, | ||
| "Use_Clock_Period_for_Unconstrainted IO" : false, | ||
| "VCCAUX" : 3.3, | ||
| "VCCX" : "3.3", | ||
| "VHDL_Standard" : "VHDL_Std_1993", | ||
| "Verilog_Standard" : "Vlg_Std_Sysv2017", | ||
| "WAKE_UP" : "0", | ||
| "Write_Vendor_Constraint_File" : true, | ||
| "show_all_warnings" : false, | ||
| "turn_off_bg" : false | ||
| } |