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Merge pull request #195 from Konf/main
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Update and refactor pipeline examples, add moving average filter examples
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@yuri-panchul
yuri-panchul authored Nov 20, 2024
2 parents 12bf210 + 995c1d5 commit 5c15b42
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64 changes: 30 additions & 34 deletions labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,67 +76,63 @@ module lab_top

//------------------------------------------------------------------------

logic [w_sw_actual-1:0] pow_input;


logic [(2*w_sw_actual)-1:0] pow_mul_stage_1;
logic [(3*w_sw_actual)-1:0] pow_mul_stage_2;
logic [(4*w_sw_actual)-1:0] pow_mul_stage_3;
logic [(5*w_sw_actual)-1:0] pow_mul_stage_4;

logic [(2*w_sw_actual)-1:0] pow_data_stage_1;
logic [(3*w_sw_actual)-1:0] pow_data_stage_2;
logic [(4*w_sw_actual)-1:0] pow_data_stage_3;
logic [(2*w_sw_actual)-1:0] pow_data_stage_1_ff;
logic [(3*w_sw_actual)-1:0] pow_data_stage_2_ff;
logic [(4*w_sw_actual)-1:0] pow_data_stage_3_ff;
logic [(5*w_sw_actual)-1:0] pow_data_stage_4_ff;

logic [w_sw_actual-1:0] pow_input_stage_1;
logic [w_sw_actual-1:0] pow_input_stage_2;
logic [w_sw_actual-1:0] pow_input_stage_3;
logic [w_sw_actual-1:0] input_stage_0_ff;
logic [w_sw_actual-1:0] input_stage_1_ff;
logic [w_sw_actual-1:0] input_stage_2_ff;
logic [w_sw_actual-1:0] input_stage_3_ff;

logic [(5*w_sw_actual)-1:0] pow_output;


// Input data pipeline
always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_input <= '0;
else
pow_input <= sw;

always_ff @ (posedge slow_clk or posedge rst)
if (rst) begin
pow_input_stage_1 <= '0;
pow_input_stage_2 <= '0;
pow_input_stage_3 <= '0;
input_stage_0_ff <= '0;
input_stage_1_ff <= '0;
input_stage_2_ff <= '0;
input_stage_3_ff <= '0;
end
else begin
pow_input_stage_1 <= pow_input;
pow_input_stage_2 <= pow_input_stage_1;
pow_input_stage_3 <= pow_input_stage_2;
input_stage_0_ff <= sw;
input_stage_1_ff <= input_stage_0_ff;
input_stage_2_ff <= input_stage_1_ff;
input_stage_3_ff <= input_stage_2_ff;
end


// Multiply numbers
assign pow_mul_stage_1 = pow_input * pow_input;
assign pow_mul_stage_2 = pow_data_stage_1 * pow_input_stage_1;
assign pow_mul_stage_3 = pow_data_stage_2 * pow_input_stage_2;
assign pow_mul_stage_4 = pow_data_stage_3 * pow_input_stage_3;
assign pow_mul_stage_1 = input_stage_0_ff * input_stage_0_ff;
assign pow_mul_stage_2 = input_stage_1_ff * pow_data_stage_1_ff;
assign pow_mul_stage_3 = input_stage_2_ff * pow_data_stage_2_ff;
assign pow_mul_stage_4 = input_stage_3_ff * pow_data_stage_3_ff;

always_ff @ (posedge slow_clk or posedge rst)
if (rst) begin
pow_data_stage_1 <= '0;
pow_data_stage_2 <= '0;
pow_data_stage_3 <= '0;
pow_data_stage_1_ff <= '0;
pow_data_stage_2_ff <= '0;
pow_data_stage_3_ff <= '0;
pow_data_stage_4_ff <= '0;
end
else begin
pow_data_stage_1 <= pow_mul_stage_1;
pow_data_stage_2 <= pow_mul_stage_2;
pow_data_stage_3 <= pow_mul_stage_3;
pow_data_stage_1_ff <= pow_mul_stage_1;
pow_data_stage_2_ff <= pow_mul_stage_2;
pow_data_stage_3_ff <= pow_mul_stage_3;
pow_data_stage_4_ff <= pow_mul_stage_4;
end

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_output <= '0;
else
pow_output <= pow_mul_stage_4;
assign pow_output = pow_data_stage_4_ff;


localparam w_display_number = w_digit * 4;
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109 changes: 53 additions & 56 deletions labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,56 +76,51 @@ module lab_top

//------------------------------------------------------------------------

logic [w_sw_actual-1:0] pow_input;


logic [(2*w_sw_actual)-1:0] pow_mul_stage_1;
logic [(3*w_sw_actual)-1:0] pow_mul_stage_2;
logic [(4*w_sw_actual)-1:0] pow_mul_stage_3;
logic [(5*w_sw_actual)-1:0] pow_mul_stage_4;

logic [(2*w_sw_actual)-1:0] pow_data_stage_1;
logic [(3*w_sw_actual)-1:0] pow_data_stage_2;
logic [(4*w_sw_actual)-1:0] pow_data_stage_3;
logic [(2*w_sw_actual)-1:0] pow_data_stage_1_ff;
logic [(3*w_sw_actual)-1:0] pow_data_stage_2_ff;
logic [(4*w_sw_actual)-1:0] pow_data_stage_3_ff;
logic [(5*w_sw_actual)-1:0] pow_data_stage_4_ff;

logic [w_sw_actual-1:0] pow_input_stage_1;
logic [w_sw_actual-1:0] pow_input_stage_2;
logic [w_sw_actual-1:0] pow_input_stage_3;
logic [w_sw_actual-1:0] input_stage_0_ff;
logic [w_sw_actual-1:0] input_stage_1_ff;
logic [w_sw_actual-1:0] input_stage_2_ff;
logic [w_sw_actual-1:0] input_stage_3_ff;

logic [(5*w_sw_actual)-1:0] pow_output;
logic data_valid_stage_0_ff;
logic data_valid_stage_1_ff;
logic data_valid_stage_2_ff;
logic data_valid_stage_3_ff;
logic data_valid_stage_4_ff;

logic [(5*w_sw_actual)-1:0] pow_output;
logic pow_output_valid;

logic input_valid;
logic data_valid_stage_1;
logic data_valid_stage_2;
logic data_valid_stage_3;
logic output_valid;


// "Valid" flags
always_ff @ (posedge slow_clk or posedge rst)
if (rst)
input_valid <= '0;
else
input_valid <= key[0];

always_ff @ (posedge slow_clk or posedge rst)
if (rst) begin
data_valid_stage_1 <= '0;
data_valid_stage_2 <= '0;
data_valid_stage_3 <= '0;
data_valid_stage_0_ff <= '0;
data_valid_stage_1_ff <= '0;
data_valid_stage_2_ff <= '0;
data_valid_stage_3_ff <= '0;
data_valid_stage_4_ff <= '0;
end
else begin
data_valid_stage_1 <= input_valid;
data_valid_stage_2 <= data_valid_stage_1;
data_valid_stage_3 <= data_valid_stage_2;
data_valid_stage_0_ff <= key[0];
data_valid_stage_1_ff <= data_valid_stage_0_ff;
data_valid_stage_2_ff <= data_valid_stage_1_ff;
data_valid_stage_3_ff <= data_valid_stage_2_ff;
data_valid_stage_4_ff <= data_valid_stage_3_ff;
end

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
output_valid <= '0;
else
output_valid <= data_valid_stage_3;


// Input data pipeline

Expand All @@ -134,63 +129,66 @@ module lab_top

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_input <= '0;
input_stage_0_ff <= '0;
else
pow_input <= sw;
input_stage_0_ff <= sw;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_input_stage_1 <= '0;
input_stage_1_ff <= '0;
else
pow_input_stage_1 <= pow_input;
input_stage_1_ff <= input_stage_0_ff;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_input_stage_2 <= '0;
input_stage_2_ff <= '0;
else
pow_input_stage_2 <= pow_input_stage_1;
input_stage_2_ff <= input_stage_1_ff;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_input_stage_3 <= '0;
input_stage_3_ff <= '0;
else
pow_input_stage_3 <= pow_input_stage_2;
input_stage_3_ff <= input_stage_2_ff;


// Multiply numbers
assign pow_mul_stage_1 = pow_input * pow_input;
assign pow_mul_stage_2 = pow_data_stage_1 * pow_input_stage_1;
assign pow_mul_stage_3 = pow_data_stage_2 * pow_input_stage_2;
assign pow_mul_stage_4 = pow_data_stage_3 * pow_input_stage_3;
assign pow_mul_stage_1 = input_stage_0_ff * input_stage_0_ff;
assign pow_mul_stage_2 = input_stage_1_ff * pow_data_stage_1_ff;
assign pow_mul_stage_3 = input_stage_2_ff * pow_data_stage_2_ff;
assign pow_mul_stage_4 = input_stage_3_ff * pow_data_stage_3_ff;


// Exercise: 1) remove unnecessary resets here to reduce ASIC area
// 2) use clock gating to reduce pipeline power consumption

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_data_stage_1 <= '0;
pow_data_stage_1_ff <= '0;
else
pow_data_stage_1 <= pow_mul_stage_1;
pow_data_stage_1_ff <= pow_mul_stage_1;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_data_stage_2 <= '0;
pow_data_stage_2_ff <= '0;
else
pow_data_stage_2 <= pow_mul_stage_2;
pow_data_stage_2_ff <= pow_mul_stage_2;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_data_stage_3 <= '0;
pow_data_stage_3_ff <= '0;
else
pow_data_stage_3 <= pow_mul_stage_3;
pow_data_stage_3_ff <= pow_mul_stage_3;

always_ff @ (posedge slow_clk or posedge rst)
if (rst)
pow_output <= '0;
pow_data_stage_4_ff <= '0;
else
pow_output <= pow_mul_stage_4;
pow_data_stage_4_ff <= pow_mul_stage_4;


assign pow_output_valid = data_valid_stage_4_ff;
assign pow_output = pow_data_stage_4_ff;

localparam w_display_number = w_digit * 4;

Expand All @@ -204,10 +202,9 @@ module lab_top
.digit ( digit )
);

assign led[0] = input_valid;
assign led[1] = data_valid_stage_1;
assign led[2] = data_valid_stage_2;
assign led[3] = data_valid_stage_3;
assign led[4] = output_valid;
assign led[0] = data_valid_stage_1_ff;
assign led[1] = data_valid_stage_2_ff;
assign led[2] = data_valid_stage_3_ff;
assign led[3] = data_valid_stage_4_ff;

endmodule
1 change: 1 addition & 0 deletions labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ module tb;
`ifdef __ICARUS__
$dumpvars;
`endif
key[3:1] = '0;

repeat (32)
begin
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