Localparam changed

yuri-panchul · Nov 22, 2024 · 2442cf6 · 2442cf6
1 parent 133ca9d
commit 2442cf6
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Showing 6 changed files with 13 additions and 101 deletions.
diff --git a/labs/3_music/3_1_note_recognizer/lab_specific_board_config.svh b/labs/3_music/3_1_note_recognizer/lab_specific_board_config.svh
diff --git a/labs/3_music/3_1_note_recognizer_tang_nano_20k/lab_specific_board_config.svh b/labs/3_music/3_1_note_recognizer_tang_nano_20k/lab_specific_board_config.svh
diff --git a/labs/3_music/3_2_melody_recognizer/lab_specific_board_config.svh b/labs/3_music/3_2_melody_recognizer/lab_specific_board_config.svh
diff --git a/labs/3_music/3_3_note_synthesizer/lab_specific_board_config.svh b/labs/3_music/3_3_note_synthesizer/lab_specific_board_config.svh
diff --git a/labs/3_music/3_4_music_player/lab_specific_board_config.svh b/labs/3_music/3_4_music_player/lab_specific_board_config.svh
diff --git a/peripherals/i2s_audio_out.sv b/peripherals/i2s_audio_out.sv
@@ -20,25 +20,27 @@ module i2s_audio_out
     output                sdata
 );
 
-    localparam MCLK_DIV = $clog2 (clk_mhz * 1000 / 12500);  // MCLK 12.288 MHz master clock
-    localparam BCLK_DIV = $clog2 (clk_mhz * 1000 / 3072);   // BCLK  3.072 MHz serial clock for a 48 KHz Sample Rate
-    localparam CLK_DIV  = $clog2 (clk_mhz * 1000 / 53  );   // LRCLK    48 KHz sampling rate for each channel
+// Standard frequencies are 12.288 MHz, 3.072 MHz and 48 KHz. 
+// We are using frequencies somewhat higher but with the same relationship 256:64:1
+    localparam MCLK_BIT   =  $clog2 (clk_mhz) - 4;
+    localparam BCLK_BIT   =  MCLK_BIT + 2;
+    localparam LRCLK_BIT  =  BCLK_BIT + 6;
 
-    logic  [CLK_DIV - 1:0] clk_div;
-    logic  [         31:0] shift;
+    logic  [LRCLK_BIT - 1:0] clk_div;
+    logic  [           31:0] shift;
 
     always_ff @ (posedge clk or posedge reset)
         if (reset)
             clk_div <= 0;
         else
             clk_div <= clk_div + 1'b1;
 
-    if (MCLK_DIV)
-        assign mclk  = clk_div [MCLK_DIV - 1];
+    if (MCLK_BIT)
+        assign mclk  = clk_div [MCLK_BIT - 1];
     else
         assign mclk  = clk_div [0];
-    assign bclk  = clk_div [BCLK_DIV - 1];
-    assign lrclk = clk_div [CLK_DIV  - 1];
+    assign bclk  = clk_div [BCLK_BIT  - 1];
+    assign lrclk = clk_div [LRCLK_BIT - 1];
 
     assign sdata = shift   [          31];
 
@@ -47,14 +49,14 @@ module i2s_audio_out
             shift <= 0;
         else
         begin
-            if (clk_div [CLK_DIV - 2:0] == { BCLK_DIV { 1'b1 } })       // 'b1111 Data front position (MSB) regarding LRCLK or WS position
+            if (clk_div [LRCLK_BIT - 2:0] == { BCLK_BIT { 1'b1 } })     // 'b1111 Data front position (MSB) regarding LRCLK or WS position
             begin
                 if (align_right)
                     shift [1  +: in_res] <= 31' (data_in);              // Put the data on the right side
                 else
                     shift [31 -: in_res] <= 32' (data_in);              // Put the data starting with the highest bytes, on the left side
             end
-            else if (clk_div [BCLK_DIV - 1:0] == { BCLK_DIV { 1'b1 } }) // 'b1111 Data end position (LSB) regarding LRCK or WS position
+            else if (clk_div [BCLK_BIT - 1:0] == { BCLK_BIT { 1'b1 } }) // 'b1111 Data end position (LSB) regarding LRCK or WS position
             begin
                 shift <= shift << 1;
             end