A collection of In-Memory-Computing papers targeting general-purpose computing and deep learning acceleration.
Keywords: IMC: In-Memory-Computing | NMC: Near-Memory-Computing
[TCS_2021] [IMC, SRAM] Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
Bibtex
@article{TCS_2021_SRAM-IMC-AI,
title={Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices},
author={Jhang, Chuan-Jia and Xue, Cheng-Xin and Hung, Je-Min and Chang, Fu-Chun and Chang, Meng-Fan},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
volume={68},
number={5},
pages={1773--1786},
year={2021},
publisher={IEEE}
}[GLVLSI_2020] [IMC] In-Memory Computing: The Next-Generation AI Computing Paradigm
Bibtex
@inproceedings{GLVLSI_2020_IMC-AI,
title={In-Memory Computing: The Next-Generation AI Computing Paradigm},
author={Ma, Yufei and Du, Yuan and Du, Li and Lin, Jun and Wang, Zhongfeng},
booktitle={Proceedings of the 2020 on Great Lakes Symposium on VLSI},
pages={265--270},
year={2020}
}[GLSVLSI_2020] [IMC] A Review of In-Memory Computing Architectures for Machine Learning Applications
Bibtex
@inproceedings{GLSVLSI_2020_IMCML,
title={A Review of In-Memory Computing Architectures for Machine Learning Applications},
author={Bavikadi, Sathwika and Sutradhar, Purab Ranjan and Khasawneh, Khaled N and Ganguly, Amlan and Pudukotai Dinakarrao, Sai Manoj},
booktitle={Proceedings of the 2020 on Great Lakes Symposium on VLSI},
pages={89--94},
year={2020}
}
[Nature_2020] [IMC] Memory devices and applications for in-memory computing
Bibtex
@article{Nature_2020_IMC_devices,
title={Memory devices and applications for in-memory computing},
author={Sebastian, Abu and Le Gallo, Manuel and Khaddam-Aljameh, Riduan and Eleftheriou, Evangelos},
journal={Nature nanotechnology},
volume={15},
number={7},
pages={529--544},
year={2020},
publisher={Nature Publishing Group}
}[DATE_2018] [IMC, STT-MRAM] Computing-in-Memory with Spintronics
Bibtex
@inproceedings{DATE_2018_CIM-Spin,
title={Computing-in-memory with spintronics},
author={Jain, Shubham and Sapatnekar, Sachin and Wang, Jian-Ping and Roy, Kaushik and Raghunathan, Anand},
booktitle={2018 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
pages={1640--1645},
year={2018},
organization={IEEE}
}[MM_2019] [NMC] Near-Memory Computing: Past, Present, and Future
Bibtex
@article{MM_2019_NMC,
title={Near-memory computing: Past, present, and future},
author={Singh, Gagandeep and Chelini, Lorenzo and Corda, Stefano and Awan, Ahsan Javed and Stuijk, Sander and Jordans, Roel and Corporaal, Henk and Boonstra, Albert-Jan},
journal={Microprocessors and Microsystems},
volume={71},
pages={102868},
year={2019},
publisher={Elsevier}
}[DSD_2018] [NMC] A Review of Near-Memory Computing Architectures: Opportunities and Challenges
Bibtex
@inproceedings{DSD_2018_NMC,
title={A review of near-memory computing architectures: Opportunities and challenges},
author={Singh, Gagandeep and Chelini, Lorenzo and Corda, Stefano and Awan, Ahsan Javed and Stuijk, Sander and Jordans, Roel and Corporaal, Henk and Boonstra, Albert-Jan},
booktitle={2018 21st Euromicro Conference on Digital System Design (DSD)},
pages={608--617},
year={2018},
organization={IEEE}
}Bibtex
Networks: BNN: Binary Neural Networks | BTN : Binary-activation Ternary-weight Networks| TBN : Ternary-activation Binary-weight Networks| TNN: Ternary Neural Networks
[DATE_2021] [SOT-MRAM, TNN] SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture
Bibtex
@INPROCEEDINGS{DATE_2021_SpinLiM,
author={Luo, Lichuan and Zhang, He and Bai, Jinyu and Zhang, Youguang and Kang, Wang and Zhao, Weisheng},
booktitle={2021 Design, Automation and Test in Europe Conference and Exhibition (DATE)},
title={SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture},
year={2021},
volume={},
number={},
pages={1865-1870},
doi={10.23919/DATE51398.2021.9474022}
}[CICC_2021] [SRAM/CMOS, TNN] An In-Memory-Computing Charge-Domain Ternary CNN Classifier
Bibtex
@inproceedings{CICC_2021_IMC-CD-TNN,
title={An In-Memory-Computing Charge-Domain Ternary CNN Classifier},
author={Yang, Xiangxing and Zhu, Keren and Tang, Xiyuan and Wang, Meizhi and Zhan, Mingtao and Lu, Nanshu and Kulkarni, Jaydeep P and Pan, David Z and Liu, Yongpan and Sun, Nan},
booktitle={2021 IEEE Custom Integrated Circuits Conference (CICC)},
pages={1--2},
year={2021},
organization={IEEE}
}[OJCAS_2021] [RRAM, BTN] A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications
Bibtex
@ARTICLE{JCAS_2021_4T2R-IM-DP,
author={Chen, Yuzong and Lu, Lu and Kim, Bongjin and Kim, Tony Tae-Hyoung},
journal={IEEE Open Journal of Circuits and Systems},
title={A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications},
year={2021},
volume={2},
number={},
pages={210-222},
doi={10.1109/OJCAS.2020.3042550}
}[ISCAS_2021] [Mem-Crossbar, Ternary Full Adder] Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars
Bibtex
@INPROCEEDINGS{ISCAS_2021_Ter-LiM,
author={Liu, Weiyi and Sun, Yanan and He, Weifeng and Wang, Qin},
booktitle={2021 IEEE International Symposium on Circuits and Systems (ISCAS)},
title={Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars},
year={2021},
volume={},
number={},
pages={1-5},
doi={10.1109/ISCAS51556.2021.9401308}
}[TVLSI_2020] [SRAM/CMOS, TNN] TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks
Bibtex
@article{TVLSI_2020_TiM-DNN,
title={TiM-DNN: Ternary in-memory accelerator for deep neural networks},
author={Jain, Shubham and Gupta, Sumeet Kumar and Raghunathan, Anand},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume={28},
number={7},
pages={1567--1577},
year={2020},
publisher={IEEE}
}[DATE_2020] [FeRAM, TNN] Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks
Bibtex
@INPROCEEDINGS{DATE_2020_TeC-Cell,
author={Thirumala, Sandeep Krishna and Jain, Shubham and Gupta, Sumeet Kumar and Raghunathan, Anand},
booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks},
year={2020},
volume={},
number={},
pages={31-36},
doi={10.23919/DATE48585.2020.9116495}
}[JSSC_2020] [SRAM, TBN+BNN ] XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
Bibtex
@article{JSSC_2020_XNOR-SRAM,
title={XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks},
author={Yin, Shihui and Jiang, Zhewei and Seo, Jae-Sun and Seok, Mingoo},
journal={IEEE Journal of Solid-State Circuits},
volume={55},
number={6},
pages={1733--1743},
year={2020},
publisher={IEEE}
}- Works From Deliang Fan's Group
[ASP-DAC_2020] [SOT-MRAM] A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks [AND, OR, NAND, NOR, MAJ, MIN, ADD]
Bibtex
@inproceedings{ASP-DAC_2020_CA-DNN-PIM,
title={A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks},
author={Yang, Li and Angizi, Shaahin and Fan, Deliang},
booktitle={2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)},
pages={313--318},
year={2020},
organization={IEEE}
}[ASP-DAC_2019] [SOT-MRAM] ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks [AND, OR, XOR, NAND, NOR, XNOR, MAJ, MIN, ADD]
Bibtex
@inproceedings{ASPDAC_2019_ParaPIM,
title={{ParaPIM}: A parallel processing-in-memory accelerator for binary-weight deep neural networks},
author={Angizi, Shaahin and He, Zhezhi and Fan, Deliang},
booktitle={Proceedings of the 24th Asia and South Pacific Design Automation Conference},
pages={127--132},
year={2019}
}[TCAD_2019] [STT-MRAM] MRIMA: An MRAM-Based In-Memory Accelerator [AND, OR, XOR, NAND, NOR, XNOR, MAJ, MIN, ADD]
Bibtex
@article{TCAD_2019_MRIMA,
title={Mrima: An mram-based in-memory accelerator},
author={Angizi, Shaahin and He, Zhezhi and Awad, Amro and Fan, Deliang},
journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
volume={39},
number={5},
pages={1123--1136},
year={2019},
publisher={IEEE}
}[DATE_2019] [SOT-MRAM, Graph Apps] GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM [AND, OR, NAND, NOR, MAJ, MIN, ADD]
Bibtex
@inproceedings{DATE_2019_GraphS,
title={GraphS: A graph processing accelerator leveraging SOT-MRAM},
author={Angizi, Shaahin and Sun, Jiao and Zhang, Wei and Fan, Deliang},
booktitle={2019 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
pages={378--383},
year={2019},
organization={IEEE}
}[NanoArch_2019] [SOT/STT-MRAM] Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach [AND, OR, NAND, NOR, MAJ, MIN, ADD]
Bibtex
@inproceedings{NanoArc_2019_ParaPIM,
title={Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach},
author={Angizi, Shaahin and Fan, Deliang},
booktitle={2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
pages={1--6},
year={2019},
organization={IEEE}
}[TCS_2019] [SRAM] A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors
Bibtex
@article{TCS_2019_SRAM,
title={A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors},
author={Si, Xin and Khwa, Win-San and Chen, Jia-Jing and Li, Jia-Fang and Sun, Xiaoyu and Liu, Rui and Yu, Shimeng and Yamauchi, Hiroyuki and Li, Qiang and Chang, Meng-Fan},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
volume={66},
number={11},
pages={4172--4185},
year={2019},
publisher={IEEE}
}[ICSICT_2018] [SRAM, RRAM] Computing-in-Memory with SRAM and RRAM for Binary Neural Networks
Bibtex
@inproceedings{ICSICT_2018_SRAM-RRAM,
title={Computing-in-memory with SRAM and RRAM for binary neural networks},
author={Sun, Xiaoyu and Liu, Rui and Peng, Xiaochen and Yu, Shimeng},
booktitle={2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)},
pages={1--4},
year={2018},
organization={IEEE}
}[JETCAS_2019] [RRAM] ReRAM-Based In-Memory Computing for Search Engine and Neural Network Applications
Bibtex
@ARTICLE{JESTCAS_2019_VR-XNOR-BNN,
author={Halawani, Yasmin and Mohammad, Baker and Abu Lebdeh, Muath and Al-Qutayri, Mahmoud and Al-Sarawi, Said F.},
journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
title={ReRAM-Based In-Memory Computing for Search Engine and Neural Network Applications},
year={2019},
volume={9},
number={2},
pages={388-397},
doi={10.1109/JETCAS.2019.2909317}
}[TACO_2019] [STT-MRAM] PIMBALL: Binary Neural Networks in Spintronic Memory
Bibtex
@article{TACO_2019_PIMBALL,
title={Pimball: Binary neural networks in spintronic memory},
author={Resch, Salonik and Khatamifard, S Karen and Chowdhury, Zamshed Iqbal and Zabihi, Masoud and Zhao, Zhengyang and Wang, Jian-Ping and Sapatnekar, Sachin S and Karpuzcu, Ulya R},
journal={ACM Transactions on Architecture and Code Optimization (TACO)},
volume={16},
number={4},
pages={1--26},
year={2019},
publisher={ACM New York, NY, USA}
}[ASP-DAC_2018] [RRAM] Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons
Bibtex
@inproceedings{ASP-DAC_2018_RRAM-BNN,
title={Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1,- 1) weights and (+ 1, 0) neurons},
author={Sun, Xiaoyu and Peng, Xiaochen and Chen, Pai-Yu and Liu, Rui and Seo, Jae-sun and Yu, Shimeng},
booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
pages={574--579},
year={2018},
organization={IEEE}
}Bibtex
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@article{TCS_2019_DRAM,
title={In-memory low-cost bit-serial addition using commodity DRAM technology},
author={Ali, Mustafa F and Jaiswal, Akhilesh and Roy, Kaushik},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
volume={67},
number={1},
pages={155--165},
year={2019},
publisher={IEEE}
}- From Purdue University
[TNano_2020] [VSH-MRAM, DVSH-MRAM] Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-Memory Support [AND, OR, XOR, NOT, NAND, NOR, ADD]
Bibtex
@article{TN_2020_VCS-CiM,
title={Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-Memory Support},
author={Thirumala, Sandeep Krishna and Hung, Yi-Tse and Jain, Shubham and Raha, Arnab and Thakuria, Niharika and Raghunathan, Vijay and Raghunathan, Anand and Chen, Zhihong and Gupta, Sumeet},
journal={IEEE Transactions on Nanotechnology},
volume={19},
pages={635--647},
year={2020},
publisher={IEEE}
}[ISLPED_2019] [R-FEFETs] Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation [AND, OR, XOR, NOT, NAND, NOR, ADD]
Bibtex
@inproceedings{ISLPED_2019_FEFET-CiM,
title={Non-volatile memory utilizing reconfigurable ferroelectric transistors to enable differential read and energy-efficient in-memory computation},
author={Thirumala, Sandeep Krishna and Jain, Shubham and Raghunathan, Anand and Gupta, Sumeet Kumar},
booktitle={2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},
pages={1--6},
year={2019},
organization={IEEE}
}[TVLSI_2017] [STT-MRAM] Computing in Memory With Spin-Transfer Torque Magnetic RAM [AND, OR, XOR, NOT, NAND, NOR, ADD, Vector Op]
Bibtex
@article{TVLSI_2017_STT-CiM,
title={Computing in memory with spin-transfer torque magnetic RAM},
author={Jain, Shubham and Ranjan, Ashish and Roy, Kaushik and Raghunathan, Anand},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
volume={26},
number={3},
pages={470--483},
year={2017},
publisher={IEEE}
}- From Other Research Groups
Bibtex
[ISCAS_2020] [GP+BNN] Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing [AND, NOR, XOR, TCAM, XNOR-popcnt]
Bibtex
@INPROCEEDINGS{ISCAS_2020_2T2R-TCAM-BNN,
author={Chen, Yuzong and Lu, Lu and Kim, Bongjin and Kim, Tony Tae-Hyoung},
booktitle={2020 IEEE International Symposium on Circuits and Systems (ISCAS)},
title={Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing},
year={2020},
volume={},
number={},
pages={1-5},
doi={10.1109/ISCAS45731.2020.9180665}
}Bibtex
[Science_2021] [FeRAM] Logic and in-memory computing achieved in a single ferroelectric semiconductor transistor [AND, OR, NAND, NOR, IMP]
Bibtex
@article{Science_2021_FeRAM,
title={Logic and in-memory computing achieved in a single ferroelectric semiconductor transistor},
author={Wang, Junjun and Wang, Feng and Wang, Zhenxing and Huang, Wenhao and Yao, Yuyu and Wang, Yanrong and Yang, Jia and Li, Ningning and Yin, Lei and Cheng, Ruiqing and others},
journal={Science Bulletin},
year={2021},
publisher={Elsevier}
}Bibtex
- Tony Tae-Hyoung Kim's group: Yuzong Chen, Lu Lu ..., Nanyang Technological University, Singapore
- Weisheng Zhao's group, Beihang University, China
- Deliang Fan's group: Shaahin Angizi ..., Arizona State University, USA
- Anand Raghunathan and Kaushik Roy's groups: Shubham Jain and Ashish Ranjan, Purdue University, USA
- Zhigang Mao and Weikang Qian's group, Shanghai Jiao Tong University, China