feat: add target riscv32im-succinct-zkvm-elf

succinctlabs · Sep 21, 2024 · 403d3f5 · 403d3f5
1 parent eeb90cd
commit 403d3f5
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Showing 10 changed files with 74 additions and 4 deletions.
diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
@@ -1748,6 +1748,7 @@ supported_targets! {
 
     ("riscv32i-unknown-none-elf", riscv32i_unknown_none_elf),
     ("riscv32im-risc0-zkvm-elf", riscv32im_risc0_zkvm_elf),
+    ("riscv32im-succinct-zkvm-elf", riscv32im_succinct_zkvm_elf),
     ("riscv32im-unknown-none-elf", riscv32im_unknown_none_elf),
     ("riscv32ima-unknown-none-elf", riscv32ima_unknown_none_elf),
     ("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),

diff --git a/compiler/rustc_target/src/spec/targets/riscv32im_succinct_zkvm_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32im_succinct_zkvm_elf.rs
@@ -0,0 +1,42 @@
+use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel};
+use crate::spec::{Target, TargetOptions};
+
+pub fn target() -> Target {
+    Target {
+        data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
+        llvm_target: "riscv32".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: Some("Succinct's zero-knowledge Virtual Machine (RV32IM ISA)".into()),
+            tier: Some(3),
+            host_tools: Some(false),
+            std: None, // ?
+        },
+        pointer_width: 32,
+        arch: "riscv32".into(),
+
+        options: TargetOptions {
+            os: "zkvm".into(),
+            vendor: "succinct".into(),
+            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
+            linker: Some("rust-lld".into()),
+            cpu: "generic-rv32".into(),
+
+            // Some crates (*cough* crossbeam) assume you have 64 bit
+            // atomics if the target name is not in a hardcoded list.
+            // Since zkvm is singlethreaded and all operations are
+            // atomic, I guess we can just say we support 64-bit
+            // atomics.
+            max_atomic_width: Some(64),
+            atomic_cas: true,
+
+            features: "+m".into(),
+            executables: true,
+            panic_strategy: PanicStrategy::Abort,
+            relocation_model: RelocModel::Static,
+            emit_debug_gdb_scripts: false,
+            eh_frame_header: false,
+            singlethread: true,
+            ..Default::default()
+        },
+    }
+}
diff --git a/library/std/src/sys/pal/zkvm/abi.rs b/library/std/src/sys/pal/zkvm/abi.rs
@@ -1,6 +1,6 @@
-//! ABI definitions for symbols exported by risc0-zkvm-platform.
+//! ABI definitions for symbols exported by zkvm platforms.
 
-// Included here so we don't have to depend on risc0-zkvm-platform.
+// Included here so we don't have to depend on zkvm platform crates.
 //
 // FIXME: Should we move this to the "libc" crate?  It seems like other
 // architectures put a lot of this kind of stuff there.  But there's
@@ -34,7 +34,10 @@ extern "C" {
         buf: *const u8,
         count: u32,
     );
+    #[cfg(target_vendor = "risc0")]
     pub fn sys_rand(recv_buf: *mut u32, words: usize);
+    #[cfg(target_vendor = "succinct")]
+    pub fn sys_rand(recv_buf: *mut u8, words: usize);
     pub fn sys_panic(msg_ptr: *const u8, len: usize) -> !;
     pub fn sys_log(msg_ptr: *const u8, len: usize);
     pub fn sys_cycle_count() -> usize;

diff --git a/library/std/src/sys/pal/zkvm/mod.rs b/library/std/src/sys/pal/zkvm/mod.rs
@@ -1,4 +1,4 @@
-//! System bindings for the risc0 zkvm platform
+//! System bindings for the zkvm platform
 //!
 //! This module contains the facade (aka platform-specific) implementations of
 //! OS level functionality for zkvm.
@@ -64,10 +64,23 @@ pub fn abort_internal() -> ! {
     core::intrinsics::abort();
 }
 
+#[cfg(target_vendor = "risc0")]
 pub fn hashmap_random_keys() -> (u64, u64) {
     let mut buf = [0u32; 4];
     unsafe {
         abi::sys_rand(buf.as_mut_ptr(), 4);
     };
     ((buf[0] as u64) << 32 + buf[1] as u64, (buf[2] as u64) << 32 + buf[3] as u64)
 }
+
+#[cfg(target_vendor = "succinct")]
+pub fn hashmap_random_keys() -> (u64, u64) {
+    let mut buf = [0u8; 16];
+    unsafe {
+        abi::sys_rand(buf.as_mut_ptr(), buf.len());
+    };
+
+    let a = u64::from_le_bytes(buf[0..8].try_into().unwrap());
+    let b = u64::from_le_bytes(buf[8..16].try_into().unwrap());
+    (a, b)
+}
diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md
@@ -63,6 +63,7 @@
     - [powerpc-unknown-openbsd](platform-support/powerpc-unknown-openbsd.md)
     - [powerpc64-ibm-aix](platform-support/aix.md)
     - [riscv32im-risc0-zkvm-elf](platform-support/riscv32im-risc0-zkvm-elf.md)
+    - [riscv32im-succinct-zkvm-elf](platform-support/riscv32im-succinct-zkvm-elf.md)
     - [riscv32imac-unknown-xous-elf](platform-support/riscv32imac-unknown-xous-elf.md)
     - [riscv32*-unknown-none-elf](platform-support/riscv32-unknown-none-elf.md)
     - [sparc-unknown-none-elf](./platform-support/sparc-unknown-none-elf.md)

diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
@@ -346,6 +346,7 @@ target | std | host | notes
 `riscv32gc-unknown-linux-gnu` |   |   | RISC-V Linux (kernel 5.4, glibc 2.33)
 `riscv32gc-unknown-linux-musl` |   |   | RISC-V Linux (kernel 5.4, musl 1.2.3 + RISCV32 support patches)
 [`riscv32im-risc0-zkvm-elf`](platform-support/riscv32im-risc0-zkvm-elf.md) | ? |  | RISC Zero's zero-knowledge Virtual Machine (RV32IM ISA)
+[`riscv32im-succinct-zkvm-elf`](platform-support/riscv32im-succinct-zkvm-elf.md) | ? |  | Succinct's zero-knowledge Virtual Machine (RV32IM ISA)
 [`riscv32ima-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * |  | Bare RISC-V (RV32IMA ISA)
 [`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? |  | RISC-V Xous (RV32IMAC ISA)
 [`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ |  | RISC-V ESP-IDF

diff --git a/src/doc/rustc/src/platform-support/riscv32im-succinct-zkvm-elf.md b/src/doc/rustc/src/platform-support/riscv32im-succinct-zkvm-elf.md
@@ -0,0 +1,5 @@
+# `riscv32im-succinct-zkvm-elf`
+
+**Tier: 3**
+
+Succinct's Zero Knowledge Virtual Machine (zkVM) implementing the RV32IM instruction set.
diff --git a/src/tools/build-manifest/src/main.rs b/src/tools/build-manifest/src/main.rs
@@ -131,6 +131,7 @@ static TARGETS: &[&str] = &[
     "powerpc64le-unknown-linux-gnu",
     "riscv32i-unknown-none-elf",
     "riscv32im-risc0-zkvm-elf",
+    "riscv32im-succinct-zkvm-elf",
     "riscv32im-unknown-none-elf",
     "riscv32ima-unknown-none-elf",
     "riscv32imc-unknown-none-elf",

diff --git a/tests/assembly/targets/targets-elf.rs b/tests/assembly/targets/targets-elf.rs
@@ -369,6 +369,9 @@
 //@ revisions: riscv32im_risc0_zkvm_elf
 //@ [riscv32im_risc0_zkvm_elf] compile-flags: --target riscv32im-risc0-zkvm-elf
 //@ [riscv32im_risc0_zkvm_elf] needs-llvm-components: riscv
+//@ revisions: riscv32im_succinct_zkvm_elf
+//@ [riscv32im_succinct_zkvm_elf] compile-flags: --target riscv32im-succinct-zkvm-elf
+//@ [riscv32im_succinct_zkvm_elf] needs-llvm-components: riscv
 //@ revisions: riscv32im_unknown_none_elf
 //@ [riscv32im_unknown_none_elf] compile-flags: --target riscv32im-unknown-none-elf
 //@ [riscv32im_unknown_none_elf] needs-llvm-components: riscv

diff --git a/tests/ui/check-cfg/well-known-values.stderr b/tests/ui/check-cfg/well-known-values.stderr
@@ -230,7 +230,7 @@ warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
 LL |     target_vendor = "_UNEXPECTED_VALUE",
    |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
-   = note: expected values for `target_vendor` are: `apple`, `espressif`, `fortanix`, `ibm`, `kmc`, `nintendo`, `nvidia`, `pc`, `risc0`, `sony`, `sun`, `unikraft`, `unknown`, `uwp`, `win7`, and `wrs`
+   = note: expected values for `target_vendor` are: `apple`, `espressif`, `fortanix`, `ibm`, `kmc`, `nintendo`, `nvidia`, `pc`, `risc0`, `sony`, `succinct`, `sun`, `unikraft`, `unknown`, `uwp`, `win7`, and `wrs`
    = note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
 
 warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`