1.2.1.9
- Use the Veditor occurences profile
- Verilog: Ignoring encrypted Verilog code, based on the protected pragma
- VHDL: Using the used packages in a file, when jumping to a declaration of this value in a package. This is avoid jumping to the wrong package when a constant is declared in multiple packages.
- VHDL: Upon detection of multiple implementations of the item you want to jump to, it provides you with a drop down menu with all the options
VHDL: Various syntax checks:
- Assigning a variable with <= instead of :=
- Assigning a signal with := instead of <=
- Using an output of an entity / procedure as input for a statement
- Assigning a value to an input or a constant