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Armv7-M: Allow register overlap in ldm + ldrd #153

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Armv7-M: Allow register overlap in ldm + ldrd #153

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0a9ac4e
fixed the register overlap
SH1E0r1r2y Jan 9, 2025
bc18688
add example for overlap
SH1E0r1r2y Jan 10, 2025
3c8dd2f
fixed the example
SH1E0r1r2y Jan 14, 2025
1825961
M7: Fix Keccak M7 code size
mkannwischer Jan 10, 2025
7ce4998
Always run CI
mkannwischer Jan 10, 2025
89e54ee
CM7: Simplify Kyber basemuls naive
dop-amin Jan 10, 2025
25aaba0
CM7: Simplify Dilithium iNTT code
dop-amin Jan 10, 2025
ec8112c
CM7: Simplify Dilithium 769 NTT code
dop-amin Jan 13, 2025
da0c503
CM7: Re-enable address offset fixup for Dilithium NTT
dop-amin Jan 13, 2025
66fab54
fixed the example.2
SH1E0r1r2y Jan 14, 2025
02dd6fe
fixed.3 & add part of examples
SH1E0r1r2y Jan 14, 2025
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22 changes: 22 additions & 0 deletions slothy/targets/arm_v7m/arch_v7m.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1940,6 +1940,16 @@ def core(inst,t,log=None):
add_comments(inst.source_line.comments)
ldr.source_line = ldr_src

ldrs_reordered = []
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for ldr, reg in zip(ldrs, regs):
if reg != ptr:
ldrs_reordered.append(ldr)

for ldr, reg in zip(ldrs, regs):
if reg == ptr:
ldrs_reordered.append(ldr)
ldrs = ldrs_reordered

if log is not None:
log(f"ldm splitting: {t.inst}; {[ldr for ldr in ldrs]}")

Expand Down Expand Up @@ -2128,6 +2138,18 @@ def core(inst,t,log=None):
add_comments(inst.source_line.comments)
ldr.source_line = ldr_src

ldrs_reordered = []
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for ldr, reg in zip(ldrs, regs):
if reg != ptr:
ldrs_reordered.append(ldr)
#log(f"inst.args_out == ptr: {reg}")
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Please remove this comment.


for ldr, reg in zip(ldrs, regs):
if reg == ptr:
ldrs_reordered.append(ldr)
#log(f"inst.args_out == ptr: {reg}")
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same here.

ldrs = ldrs_reordered

if log is not None:
log(f"ldrd splitting: {t.inst}; {[ldr for ldr in ldrs]}")

Expand Down