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Move to SystemVerilog HDL (#11)
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cmomin authored Oct 21, 2024
1 parent 7ebbe9a commit d3145d9
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Showing 27 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions Makefile
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Expand Up @@ -89,14 +89,14 @@ formal-tests: $(FORMAL_VERIF_DONE)
# VERILATOR
LINT_VERILATOR=$(DIR_HDL)/.lint-verilator
$(LINT_VERILATOR): $(HDL_DONE)
@set e; (cd $(DIR_HDL) && verilator --lint-only smaesh_hpc.v && touch $(LINT_VERILATOR) || exit 1)
@set e; (cd $(DIR_HDL) && verilator --lint-only smaesh_hpc.sv && touch $(LINT_VERILATOR) || exit 1)

lint-verilator: $(LINT_VERILATOR)
# VERIBLE
VERIBLE?=verible-verilog-lint
LINT_VERIBLE=$(DIR_HDL)/.lint-verible
$(LINT_VERIBLE): $(HDL_DONE)
@set e; ($(VERIBLE) $(DIR_HDL)/*.v --rules -parameter-name-style,-always-comb && touch $(LINT_VERIBLE) || exit 1)
@set e; ($(VERIBLE) $(DIR_HDL)/*.v $(DIR_HDL)/*.sv --rules -parameter-name-style,-always-comb && touch $(LINT_VERIBLE) || exit 1)

lint-verible: $(LINT_VERIBLE)
# lint all
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2 changes: 1 addition & 1 deletion formal_verif/Makefile
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Expand Up @@ -49,7 +49,7 @@ export TOPLEVEL_LANG ?= verilog
export SIM_BUILD ?= $(WORK_SYNTH)
# Sources related
export VERILOG_INCLUDE_DIRS?= $(HDL_DIR)
export VERILOG_SOURCES ?= $(SYNTH_NETLIST_VERILOG) $(HDL_DIR)/smaesh_hpc.v
export VERILOG_SOURCES ?= $(SYNTH_NETLIST_VERILOG) $(HDL_DIR)/smaesh_hpc.sv
# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
export TOPLEVEL ?= smaesh_hpc
# MODULE is the basename of the Python test file
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2 changes: 1 addition & 1 deletion formal_verif/synth.tcl
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Expand Up @@ -3,7 +3,7 @@ set MAIN_MODULE $::env(MAIN_MODULE)
set OUT_DIR $::env(OUT_DIR)
set MATCHI_CELLS $::env(MATCHI_CELLS)

set MAIN_PATH $IMPLEM_DIR/$MAIN_MODULE.v
set MAIN_PATH $IMPLEM_DIR/$MAIN_MODULE.sv
set LIB $MATCHI_CELLS
set LIB_V $LIB.v
set LIB $LIB.lib
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2 changes: 1 addition & 1 deletion func_tests/Makefile
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Expand Up @@ -19,7 +19,7 @@ export TOPLEVEL_LANG ?= verilog
export SIM_BUILD ?= $(WORK_CASE)
# Sources related
export VERILOG_INCLUDE_DIRS?= $(RTL_DIR_HDL)
export VERILOG_SOURCES ?= $(RTL_DIR_HDL)/*.v
export VERILOG_SOURCES ?= $(RTL_DIR_HDL)/*.v $(RTL_DIR_HDL)/*.sv
# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
export TOPLEVEL ?= smaesh_hpc
# MODULE is the basename of the Python test file
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2 changes: 1 addition & 1 deletion gather_sources.sh
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Expand Up @@ -16,7 +16,7 @@ mkdir -p $OUT_DIR
# Iterate over each directory
for var in "$@"; do
dir="$SCRIPT_DIR/$var"
files=$(find $dir -name '*.v' -o -name '*.vh')
files=$(find $dir -name '*.v' -o -name '*.vh' -o -name '*.sv')
for file in $files; do
cp $file $OUT_DIR
echo "$file copied to $OUT_DIR"
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