Merge branch 'main' into big-int-as-float

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "simd-json"
-version = "0.13.4"
+version = "0.13.6"
 authors = ["Heinz N. Gies <[email protected]>", "Sunny Gleason"]
 edition = "2021"
 exclude = ["data/*", "fuzz/*"]

src/impls/native/stage1.rs

@@ -445,6 +445,13 @@ impl Stage1Parse for SimdInput {
         base.reserve(64);
         let final_len = l + cnt;
 
+        let is_unaligned = l % 4 != 0;
+        let write_fn = if is_unaligned {
+            std::ptr::write_unaligned
+        } else {
+            std::ptr::write
+        };
+
         while bits != 0 {
             let v0 = bits.trailing_zeros() as i32;
             bits &= bits.wrapping_sub(1);
@@ -461,7 +468,7 @@ impl Stage1Parse for SimdInput {
                 idx_64_v[2] + v2,
                 idx_64_v[3] + v3,
             ];
-            std::ptr::write(base.as_mut_ptr().add(l).cast::<[i32; 4]>(), v);
+            write_fn(base.as_mut_ptr().add(l).cast::<[i32; 4]>(), v);
             l += 4;
         }
         // We have written all the data

src/impls/neon/stage1.rs

@@ -190,6 +190,13 @@ impl Stage1Parse for SimdInput {
         base.reserve(64);
         let final_len = l + cnt;
 
+        let is_unaligned = l % 4 != 0;
+        let write_fn = if is_unaligned {
+            std::ptr::write_unaligned
+        } else {
+            std::ptr::write
+        };
+
         while bits != 0 {
             let v0 = bits.trailing_zeros() as i32;
             bits &= bits.wrapping_sub(1);
@@ -202,7 +209,7 @@ impl Stage1Parse for SimdInput {
 
             let v: int32x4_t = mem::transmute([v0, v1, v2, v3]);
             let v: int32x4_t = vaddq_s32(idx_64_v, v);
-            std::ptr::write(base.as_mut_ptr().add(l).cast::<int32x4_t>(), v);
+            write_fn(base.as_mut_ptr().add(l).cast::<int32x4_t>(), v);
             l += 4;
         }
         // We have written all the data