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Add SPI2/SPI3 config and init, update default flash size
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sfxfs committed Nov 12, 2024
1 parent 5970eb6 commit 78b9372
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Showing 4 changed files with 80 additions and 6 deletions.
41 changes: 41 additions & 0 deletions components/sub_bus_init/Kconfig.projbuild
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,47 @@ menu "SUB:Bus Interface"
endmenu

menu "Interface SPI"
menu "SPI2 Config"
config SUB_ENABLE_SPI2
bool "Enable interface"
default n
depends on SOC_GPSPI_SUPPORTED

if SUB_ENABLE_SPI2
config SUB_SPI2_CLK_PIN
int "Set CLK pin num"
default 10

config SUB_SPI2_MOSI_PIN
int "Set MOSI pin num"
default 11

config SUB_SPI2_MISO_PIN
int "Set MISO pin num"
default 12
endif
endmenu

menu "SPI3 Config"
config SUB_ENABLE_SPI3
bool "Enable interface"
default n
depends on SOC_GPSPI_SUPPORTED

if SUB_ENABLE_SPI3
config SUB_SPI3_CLK_PIN
int "Set CLK pin num"
default 13

config SUB_SPI3_MOSI_PIN
int "Set MOSI pin num"
default 14

config SUB_SPI3_MISO_PIN
int "Set MISO pin num"
default 15
endif
endmenu
endmenu

endmenu
12 changes: 6 additions & 6 deletions components/sub_bus_init/sub_i2c.c
Original file line number Diff line number Diff line change
Expand Up @@ -16,24 +16,24 @@ esp_err_t sub_i2c_intf_init()
#if CONFIG_SUB_ENABLE_I2C0
{
i2c_master_bus_config_t i2c_bus_config = {
.i2c_port = 0,
.sda_io_num = CONFIG_SUB_I2C0_SDA_PIN,
.scl_io_num = CONFIG_SUB_I2C0_SCL_PIN,
.clk_source = I2C_CLK_SRC_DEFAULT,
.glitch_ignore_cnt = 7,
};
i2c_bus_config.i2c_port = 0;
i2c_bus_config.scl_io_num = CONFIG_SUB_I2C0_SCL_PIN;
i2c_bus_config.sda_io_num = CONFIG_SUB_I2C0_SDA_PIN;
ret += i2c_new_master_bus(&i2c_bus_config, &i2c0_bus_handle);
}
#endif
#if CONFIG_SUB_ENABLE_I2C1
{
i2c_master_bus_config_t i2c_bus_config = {
.i2c_port = 1,
.sda_io_num = CONFIG_SUB_I2C1_SDA_PIN,
.scl_io_num = CONFIG_SUB_I2C1_SCL_PIN,
.clk_source = I2C_CLK_SRC_DEFAULT,
.glitch_ignore_cnt = 7,
};
i2c_bus_config.i2c_port = 1;
i2c_bus_config.scl_io_num = CONFIG_SUB_I2C1_SCL_PIN;
i2c_bus_config.sda_io_num = CONFIG_SUB_I2C1_SDA_PIN;
ret += i2c_new_master_bus(&i2c_bus_config, &i2c1_bus_handle);
}
#endif
Expand Down
32 changes: 32 additions & 0 deletions components/sub_bus_init/sub_spi.c
Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,43 @@
esp_err_t sub_spi_intf_init(void)
{
esp_err_t ret = ESP_OK;
#if CONFIG_SUB_ENABLE_SPI2
{
spi_bus_config_t buscfg = {
.miso_io_num = CONFIG_SUB_SPI2_MISO_PIN,
.mosi_io_num = CONFIG_SUB_SPI2_MOSI_PIN,
.sclk_io_num = CONFIG_SUB_SPI2_CLK_PIN,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
.max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE,
};
ret += spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO);
}
#endif
#if CONFIG_SUB_ENABLE_SPI3
{
spi_bus_config_t buscfg = {
.miso_io_num = CONFIG_SUB_SPI3_MISO_PIN,
.mosi_io_num = CONFIG_SUB_SPI3_MOSI_PIN,
.sclk_io_num = CONFIG_SUB_SPI3_CLK_PIN,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
.max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE,
};
ret += spi_bus_initialize(SPI3_HOST, &buscfg, SPI_DMA_CH_AUTO);
}
#endif
return ret;
}

esp_err_t sub_spi_intf_deinit(void)
{
esp_err_t ret = ESP_OK;
#if CONFIG_SUB_ENABLE_SPI2
ret += spi_bus_free(SPI2_HOST);
#endif
#if CONFIG_SUB_ENABLE_SPI3
ret += spi_bus_free(SPI3_HOST);
#endif
return ret;
}
1 change: 1 addition & 0 deletions sdkconfig.defaults
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
#
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_sub.csv"

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