Merge pull request #909 from romancardenas/master

Add `mtvec_align` for RISC-V

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 
 ## [Unreleased]
 
+- Add `mtvec_align` field to `riscv_config` to configure the byte alignment of interrupt vector table.
 - Fix reexport path when "%s" inside "derivedFrom"
 - Force using rust edition 2021 in CI
 - Added lifetime ellision for `FieldWriter` where the explicit lifetimes are not necessary, which

src/config.rs

@@ -1,5 +1,5 @@
 use anyhow::{bail, Result};
-use proc_macro2::Span;
+use proc_macro2::{Span, TokenStream};
 use std::{
     collections::HashMap,
     ops::{Deref, DerefMut},
@@ -46,6 +46,12 @@ pub struct Config {
     pub settings: Settings,
 }
 
+impl Config {
+    pub fn extra_build(&self) -> Option<TokenStream> {
+        self.settings.extra_build()
+    }
+}
+
 #[allow(clippy::upper_case_acronyms)]
 #[allow(non_camel_case_types)]
 #[cfg_attr(feature = "serde", derive(serde::Deserialize, serde::Serialize))]
@@ -345,6 +351,10 @@ impl Settings {
             self.riscv_config = source.riscv_config;
         }
     }
+
+    pub fn extra_build(&self) -> Option<TokenStream> {
+        self.riscv_config.as_ref().and_then(|cfg| cfg.extra_build())
+    }
 }
 
 #[derive(Clone, PartialEq, Eq, Debug)]

src/config/riscv.rs

@@ -1,3 +1,6 @@
+use proc_macro2::TokenStream;
+use quote::quote;
+
 #[cfg_attr(feature = "serde", derive(serde::Deserialize), serde(default))]
 #[derive(Clone, PartialEq, Eq, Debug, Default)]
 #[non_exhaustive]
@@ -8,6 +11,22 @@ pub struct RiscvConfig {
     pub harts: Vec<RiscvEnumItem>,
     pub clint: Option<RiscvClintConfig>,
     pub plic: Option<RiscvPlicConfig>,
+    pub mtvec_align: Option<usize>,
+}
+
+impl RiscvConfig {
+    pub fn extra_build(&self) -> Option<TokenStream> {
+        self.mtvec_align.map(|align| {
+            quote! {
+                // set environment variable RISCV_MTVEC_ALIGN enfoce correct byte alignment of interrupt vector.
+                println!(
+                    "cargo:rustc-env=RISCV_MTVEC_ALIGN={}",
+                    #align
+                );
+                println!("cargo:rerun-if-env-changed=RISCV_MTVEC_ALIGN");
+            }
+        })
+    }
 }
 
 #[cfg_attr(feature = "serde", derive(serde::Deserialize), serde(default))]

src/lib.rs

@@ -671,7 +671,7 @@ pub fn generate(input: &str, config: &Config) -> Result<Generation> {
     } else {
         Some(DeviceSpecific {
             device_x,
-            build_rs: util::build_rs().to_string(),
+            build_rs: util::build_rs(&config).to_string(),
         })
     };
 

src/main.rs

@@ -366,7 +366,11 @@ Ignore this option if you are not building your own FPGA based soft-cores."),
     .contains(&config.target)
     {
         writeln!(File::create(path.join("device.x"))?, "{device_x}")?;
-        writeln!(File::create(path.join("build.rs"))?, "{}", build_rs())?;
+        writeln!(
+            File::create(path.join("build.rs"))?,
+            "{}",
+            build_rs(&config)
+        )?;
     }
 
     if config.feature_group || config.feature_peripheral {

src/util.rs

@@ -399,7 +399,9 @@ impl U32Ext for u32 {
     }
 }
 
-pub fn build_rs() -> TokenStream {
+pub fn build_rs(config: &Config) -> TokenStream {
+    let extra_build = config.extra_build();
+
     quote! {
         //! Builder file for Peripheral access crate generated by svd2rust tool
 
@@ -419,6 +421,8 @@ pub fn build_rs() -> TokenStream {
                 println!("cargo:rustc-link-search={}", out.display());
 
                 println!("cargo:rerun-if-changed=device.x");
+
+                #extra_build
             }
 
             println!("cargo:rerun-if-changed=build.rs");