Update riscv CI to 0.12.1

rust-embedded · Oct 21, 2024 · 7468bd6 · 7468bd6
1 parent 90ef2a6
commit 7468bd6
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Showing 3 changed files with 28 additions and 10 deletions.
diff --git a/ci/script.sh b/ci/script.sh
@@ -498,10 +498,10 @@ main() {
             echo 'version = "1.0.0"' >> $td/Cargo.toml
 
             echo '[dependencies.riscv]' >> $td/Cargo.toml
-            echo 'version = "0.6.0"' >> $td/Cargo.toml
+            echo 'version = "0.12.1"' >> $td/Cargo.toml
 
             echo '[dependencies.riscv-rt]' >> $td/Cargo.toml
-            echo 'version = "0.8.0"' >> $td/Cargo.toml
+            echo 'version = "0.13.0"' >> $td/Cargo.toml
 
             test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd
             test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/k210-pac/master/k210.svd

diff --git a/ci/svd2rust-regress/src/svd_test.rs b/ci/svd2rust-regress/src/svd_test.rs
@@ -16,7 +16,7 @@ const CRATES_MSP430: &[&str] = &["msp430 = \"0.4.0\"", "msp430-rt = \"0.4.0\""];
 const CRATES_ATOMICS: &[&str] =
     &["portable-atomic = { version = \"0.3.16\", default-features = false }"];
 const CRATES_CORTEX_M: &[&str] = &["cortex-m = \"0.7.6\"", "cortex-m-rt = \"0.6.13\""];
-const CRATES_RISCV: &[&str] = &["riscv = \"0.9.0\"", "riscv-rt = \"0.9.0\""];
+const CRATES_RISCV: &[&str] = &["riscv = \"0.12.1\"", "riscv-rt = \"0.13.0\""];
 const CRATES_XTENSALX: &[&str] = &["xtensa-lx-rt = \"0.9.0\"", "xtensa-lx = \"0.6.0\""];
 const CRATES_MIPS: &[&str] = &["mips-mcu = \"0.1.0\""];
 const PROFILE_ALL: &[&str] = &["[profile.dev]", "incremental = false"];

diff --git a/src/generate/device.rs b/src/generate/device.rs
@@ -2,12 +2,12 @@ use crate::svd::{array::names, Device, Peripheral};
 use proc_macro2::{Span, TokenStream};
 use quote::{quote, ToTokens};
 
-use log::debug;
+use log::{debug, warn};
 use std::fs::File;
 use std::io::Write;
 use std::path::Path;
 
-use crate::config::{Config, Settings, Target};
+use crate::config::{Config, Target};
 use crate::util::{self, ident};
 use anyhow::{Context, Result};
 
@@ -31,9 +31,9 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
     let settings = match config.settings.as_ref() {
         Some(settings) => {
             let file = std::fs::read_to_string(settings).context("could not read settings file")?;
-            serde_yaml::from_str(&file).context("could not parse settings file")?
+            Some(serde_yaml::from_str(&file).context("could not parse settings file")?)
         }
-        None => Settings::default(),
+        None => None,
     };
 
     if config.target == Target::Msp430 {
@@ -197,8 +197,23 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
 
     match config.target {
         Target::RISCV => {
-            debug!("Rendering RISC-V specific code");
-            out.extend(riscv::render(&d.peripherals, device_x, &settings)?);
+            if settings.is_none() {
+                warn!("No settings file provided for RISC-V target. Using legacy interrupts rendering");
+                warn!("Please, consider migrating your PAC to riscv 0.12.0 or later");
+                out.extend(interrupt::render(
+                    config.target,
+                    &d.peripherals,
+                    device_x,
+                    config,
+                )?);
+            } else {
+                debug!("Rendering RISC-V specific code");
+                out.extend(riscv::render(
+                    &d.peripherals,
+                    device_x,
+                    settings.as_ref().unwrap(),
+                )?);
+            }
         }
         _ => {
             debug!("Rendering interrupts");
@@ -219,7 +234,10 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
             // Core peripherals are handled above
             continue;
         }
-        if config.target == Target::RISCV && riscv::is_riscv_peripheral(p, &settings) {
+        if config.target == Target::RISCV
+            && settings.is_some()
+            && riscv::is_riscv_peripheral(p, settings.as_ref().unwrap())
+        {
             // RISC-V specific peripherals are handled above
             continue;
         }