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Add mecall backend
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romancardenas committed Jan 28, 2025
1 parent e225030 commit 9699c36
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Showing 4 changed files with 25 additions and 20 deletions.
28 changes: 19 additions & 9 deletions examples/hifive1/Cargo.lock

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4 changes: 2 additions & 2 deletions examples/hifive1/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,11 @@ edition = "2021"
[dependencies]
rtic = { path = "../../rtic" }
heapless = { version = "0.8.0", features = ["portable-atomic-unsafe-assume-single-core"] }
hifive1 = { git = "https://github.com/riscv-rust/e310x.git", branch = "ehv1", features = ["board-redv"] }
hifive1 = { version = "0.13.0", features = ["board-redv"] }
riscv-rt = {version = "0.13.0", features = ["single-hart"]}
riscv = "0.12.1"
semihosting = { version = "0.1", features = ["stdio", "panic-handler"] }
portable-atomic = { version = "1.9", features = ["unsafe-assume-single-core", "force-amo"] }
portable-atomic = { version = "1", features = ["unsafe-assume-single-core", "force-amo"] }

[features]
riscv-clint-backend = ["rtic/riscv-clint-backend"]
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7 changes: 1 addition & 6 deletions rtic-macros/src/codegen/bindings/riscv_slic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -108,10 +108,6 @@ pub fn pre_init_checks(app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream
pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
let mut stmts = vec![];

// First, we reset and disable all the interrupt controllers
stmts.push(quote!(rtic::export::clear_interrupts();));

// Then, we set the corresponding priorities
let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
for (&p, name) in interrupt_ids.chain(
app.hardware_tasks
Expand All @@ -122,8 +118,7 @@ pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<
rtic::export::set_priority(slic::SoftwareInterrupt::#name, #p);
));
}
// Finally, we activate the interrupts
stmts.push(quote!(rtic::export::set_interrupts();));

stmts
}

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6 changes: 3 additions & 3 deletions rtic/src/export/slic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,16 +7,16 @@ pub use riscv_slic::{lock, pend, run, InterruptNumber};
compile_error!("Building for the riscv-slic, but no compatible backend selected");

/// USE CASE RE-EXPORTS: needed for SLIC-only
pub use riscv_slic::{self, clear_interrupts, codegen, set_interrupts, set_priority};
pub use riscv_slic::{self, codegen, set_priority};

pub mod interrupt {
#[inline]
pub fn disable() {
riscv_slic::disable();
riscv_slic::clear_interrupts();
}

#[inline]
pub unsafe fn enable() {
riscv_slic::set_interrupts();
riscv_slic::enable();
}
}

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