timer: Take &ReferenceClock rather than &ClocksManager

ClocksManager may have been de-structured by the time a timer is created.
The source of the Timer is the ref-clock (shared with the watchdog).

rp2040-hal/examples/adc_fifo_dma.rs

@@ -146,7 +146,7 @@ fn main() -> ! {
     adc_fifo.resume();
 
     // initialize a timer, to measure the total sampling time (printed below)
-    let timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks);
+    let timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks.reference_clock);
 
     // NOTE: in a real-world program, instead of calling `wait` now, you would probably:
     // 1. Enable one of the DMA interrupts for the channel (e.g. `dma.ch0.enable_irq0()`)

rp2040-hal/examples/adc_fifo_poll.rs

@@ -133,7 +133,7 @@ fn main() -> ! {
     let mut i = 0;
 
     // initialize a timer, to measure the total sampling time (printed below)
-    let timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks);
+    let timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks.reference_clock);
 
     loop {
         // busy-wait until the FIFO contains at least two samples:

rp2040-hal/examples/blinky.rs

@@ -64,7 +64,7 @@ fn main() -> ! {
     .ok()
     .unwrap();
 
-    let mut timer = rp2040_hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks);
+    let mut timer = rp2040_hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks.reference_clock);
 
     // The single-cycle I/O block controls our GPIO pins
     let sio = hal::Sio::new(pac.SIO);

rp2040-hal/examples/vector_table.rs

@@ -110,7 +110,7 @@ fn main() -> ! {
     // Configure GPIO25 as an output
     let led_pin = pins.gpio25.into_push_pull_output();
 
-    let mut timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks);
+    let mut timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS, &clocks.reference_clock);
     critical_section::with(|cs| {
         let mut alarm = timer.alarm_0().unwrap();
         // Schedule an alarm in 1 second

rp2040-hal/src/timer.rs

@@ -13,7 +13,7 @@ use fugit::{MicrosDurationU32, MicrosDurationU64, TimerInstantU64};
 
 use crate::{
     atomic_register_access::{write_bitmask_clear, write_bitmask_set},
-    clocks::ClocksManager,
+    clocks::ReferenceClock,
     pac::{self, RESETS, TIMER},
     resets::SubsystemReset,
     typelevel::Sealed,
@@ -59,7 +59,7 @@ impl Timer {
     /// Make sure that clocks and watchdog are configured, so
     /// that timer ticks happen at a frequency of 1MHz.
     /// Otherwise, `Timer` won't work as expected.
-    pub fn new(timer: TIMER, resets: &mut RESETS, _clocks: &ClocksManager) -> Self {
+    pub fn new(timer: TIMER, resets: &mut RESETS, _clocks: &ReferenceClock) -> Self {
         timer.reset_bring_down(resets);
         timer.reset_bring_up(resets);
         Self { _private: () }