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Lean: Memory model #965

Merged
merged 24 commits into from
Feb 13, 2025
Merged

Lean: Memory model #965

merged 24 commits into from
Feb 13, 2025

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lfrenot
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@lfrenot lfrenot commented Feb 10, 2025

This closes #959

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github-actions bot commented Feb 10, 2025

Test Results

   12 files  ±0     26 suites  ±0   0s ⏱️ ±0s
  766 tests +1    766 ✅ +1  0 💤 ±0  0 ❌ ±0 
2 711 runs  +1  2 711 ✅ +1  0 💤 ±0  0 ❌ ±0 

Results for commit 7e1df36. ± Comparison against base commit 1013bd2.

♻️ This comment has been updated with latest results.

@lfrenot lfrenot marked this pull request as draft February 10, 2025 15:14
@lfrenot lfrenot changed the title Lean: class Arch Lean: Memory model Feb 10, 2025
@tobiasgrosser tobiasgrosser added the Lean Issues with Sail to Lean translation label Feb 10, 2025
@@ -80,4 +148,5 @@ def addInt {w : Nat} (x : BitVec w) (i : Int) : BitVec w :=
x + BitVec.ofInt w i

end BitVec

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This is unrelated. Do we want to change this?

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No we don't, I've removed it

@lfrenot lfrenot marked this pull request as ready for review February 10, 2025 17:43
Comment on lines 178 to 182
def write_byte (value : BitVec 8) (addr : Nat) : PreSailM RegisterType c PUnit := do
modify fun s => { s with mem := s.mem.insert addr value }
pure ()

def write_bytes (addr : Nat) (value : BitVec (8 * n)) : PreSailM RegisterType c Bool := do
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The two arguments are in the opposite order in the two functions

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Thanks, fixed

@lfrenot
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lfrenot commented Feb 11, 2025

Should I add SailTinyArm as a CI test to this PR?

@ineol
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ineol commented Feb 11, 2025

Should I add SailTinyArm as a CI test to this PR?

Let's try!

@lfrenot
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lfrenot commented Feb 11, 2025

Not sure why it is failing, it works on my end

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lfrenot commented Feb 11, 2025

I think I found it, needed to add the changes from removing the lits from function arguments

match size with
| 0 => pure (default, some true)
| n + 1 => do
let b ← read_byte addr
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I don't think the do block should get an extra indentation here.

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Done
I've also renamed the internal functions to camelCase

pure true

def sail_mem_write [Arch] (req : Mem_write_request n vasize (BitVec pa_size) ts arch) : PreSailM RegisterType c (Result (Option Bool) Arch.abort) := do
let addr := req.pa.toNat
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Where does this toNat comes from?

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the type of req in the argument fixes req.pa to be a BitVec pa_size
So that toNat is BitVec.toNat


def readBytes (size : Nat) (addr : Nat) : PreSailM RegisterType c ((BitVec (8 * size)) × Option Bool) :=
match size with
| 0 => pure (default, some true)
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In theory, the Option Bool of a memory read is only used if you want to read a tag (the tag field of the request is true) otherwise it should be none, but it's not really important, and I don't think sail code that does not want a tag will crash if you return some true

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Fixed

@bacam bacam merged commit c425694 into rems-project:sail2 Feb 13, 2025
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sail-to-lean: Add support to memory
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