PCI: read full 64-bit size of 64-bit memory BARs

examples/aarch64/src/main.rs

@@ -418,6 +418,13 @@ fn allocate_bars(
             address_type, size, ..
         } = info
         {
+            // For now, only attempt to allocate 32-bit memory regions.
+            if size > u32::MAX.into() {
+                warn!("Skipping BAR {} with size {:#x}", bar_index, size);
+                continue;
+            }
+            let size = size as u32;
+
             match address_type {
                 MemoryBarType::Width32 => {
                     if size > 0 {

src/transport/pci.rs

@@ -436,7 +436,7 @@ fn get_bar_region<H: Hal, T, C: ConfigurationAccess>(
     if bar_address == 0 {
         return Err(VirtioPciError::BarNotAllocated(struct_info.bar));
     }
-    if struct_info.offset + struct_info.length > bar_size
+    if u64::from(struct_info.offset + struct_info.length) > bar_size
         || size_of::<T>() > struct_info.length as usize
     {
         return Err(VirtioPciError::BarOffsetOutOfRange);

src/transport/pci/bus.rs

@@ -123,11 +123,11 @@
     pub fn cam_offset(self, device_function: DeviceFunction, register_offset: u8) -> u32 {
         assert!(device_function.valid());
 
         let bdf = (device_function.bus as u32) << 8
             | (device_function.device as u32) << 3
             | device_function.function as u32;
         let address =
             bdf << match self {
                 Cam::MmioCam => 8,
                 Cam::Ecam => 12,
             } | register_offset as u32;
@@ -212,6 +212,13 @@
         device_function: DeviceFunction,
         bar_index: u8,
     ) -> Result<BarInfo, PciError> {
+        // Disable address decoding while sizing the BAR.
+        let (_status, command_orig) = self.get_status_command(device_function);
+        let command_disable_decode = command_orig & !(Command::IO_SPACE | Command::MEMORY_SPACE);
+        if command_disable_decode != command_orig {
+            self.set_command(device_function, command_disable_decode);
+        }
+
         let bar_orig = self
             .configuration_access
             .read_word(device_function, BAR0_OFFSET + 4 * bar_index);
@@ -222,12 +229,41 @@
             BAR0_OFFSET + 4 * bar_index,
             0xffffffff,
         );
-        let size_mask = self
-            .configuration_access
-            .read_word(device_function, BAR0_OFFSET + 4 * bar_index);
+        let mut size_mask = u64::from(
+            self.configuration_access
+                .read_word(device_function, BAR0_OFFSET + 4 * bar_index),
+        );
+
+        // Read the upper 32 bits of 64-bit memory BARs.
+        let (address_top, size_top) = if bar_orig & 0b111 == 0b100 {
+            if bar_index >= 5 {
+                return Err(PciError::InvalidBarType);
+            }
+            let bar_top_orig = self
+                .configuration_access
+                .read_word(device_function, BAR0_OFFSET + 4 * (bar_index + 1));
+            self.configuration_access.write_word(
+                device_function,
+                BAR0_OFFSET + 4 * (bar_index + 1),
+                0xffffffff,
+            );
+            let size_top = self
+                .configuration_access
+                .read_word(device_function, BAR0_OFFSET + 4 * (bar_index + 1));
+            self.configuration_access.write_word(
+                device_function,
+                BAR0_OFFSET + 4 * (bar_index + 1),
+                bar_top_orig,
+            );
+            (bar_top_orig, size_top)
+        } else {
+            (0, 0xffffffff)
+        };
+        size_mask |= u64::from(size_top) << 32;
+
         // A wrapping add is necessary to correctly handle the case of unused BARs, which read back
         // as 0, and should be treated as size 0.
-        let size = (!(size_mask & 0xfffffff0)).wrapping_add(1);
+        let size = (!(size_mask & !0b1111)).wrapping_add(1);
 
         // Restore the original value.
         self.configuration_access.write_word(
@@ -236,24 +272,22 @@
             bar_orig,
         );
 
+        if command_disable_decode != command_orig {
+            self.set_command(device_function, command_orig);
+        }
+
         if bar_orig & 0x00000001 == 0x00000001 {
             // I/O space
             let address = bar_orig & 0xfffffffc;
-            Ok(BarInfo::IO { address, size })
+            Ok(BarInfo::IO {
+                address,
+                size: size as u32,
+            })
         } else {
             // Memory space
-            let mut address = u64::from(bar_orig & 0xfffffff0);
+            let address = u64::from(bar_orig & 0xfffffff0) | (u64::from(address_top) << 32);
             let prefetchable = bar_orig & 0x00000008 != 0;
             let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?;
-            if address_type == MemoryBarType::Width64 {
-                if bar_index >= 5 {
-                    return Err(PciError::InvalidBarType);
-                }
-                let address_top = self
-                    .configuration_access
-                    .read_word(device_function, BAR0_OFFSET + 4 * (bar_index + 1));
-                address |= u64::from(address_top) << 32;
-            }
             Ok(BarInfo::Memory {
                 address_type,
                 prefetchable,
@@ -389,7 +423,7 @@
         /// The memory address, always 16-byte aligned.
         address: u64,
         /// The size of the BAR in bytes.
-        size: u32,
+        size: u64,
     },
     /// The BAR is for an I/O region.
     IO {
@@ -415,7 +449,7 @@
 
     /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO
     /// BAR.
-    pub fn memory_address_size(&self) -> Option<(u64, u32)> {
+    pub fn memory_address_size(&self) -> Option<(u64, u64)> {
         if let Self::Memory { address, size, .. } = self {
             Some((*address, *size))
         } else {

src/transport/x86_64.rs

@@ -163,7 +163,7 @@
         let device_features_low: u32 = configread!(self.common_cfg, device_feature);
         configwrite!(self.common_cfg, device_feature_select, 1u32);
         let device_features_high: u32 = configread!(self.common_cfg, device_feature);
         (device_features_high as u64) << 32 | device_features_low as u64
     }
 
     fn write_driver_features(&mut self, driver_features: u64) {
@@ -295,7 +295,7 @@
     if bar_address == 0 {
         return Err(VirtioPciError::BarNotAllocated(struct_info.bar));
     }
-    if struct_info.offset + struct_info.length > bar_size
+    if u64::from(struct_info.offset + struct_info.length) > bar_size
         || size_of::<T>() > struct_info.length as usize
     {
         return Err(VirtioPciError::BarOffsetOutOfRange);