PCI: disable I/O and memory decode during BAR sizing

Reprogramming the BAR address to an all-1s value when attempting to
decipher which bits are writable can result in the PCI device actually
intercepting memory or I/O accesses to the resulting address. To avoid
this, disable the I/O and memory bits in the control register during the
BAR sizing process, as recommended by the PCI specification.

Fixes GitHub issue #176.

src/transport/pci/bus.rs

@@ -212,6 +212,13 @@ impl<C: ConfigurationAccess> PciRoot<C> {
         device_function: DeviceFunction,
         bar_index: u8,
     ) -> Result<BarInfo, PciError> {
+        // Disable address decoding while sizing the BAR.
+        let (_status, command_orig) = self.get_status_command(device_function);
+        let command_disable_decode = command_orig & !(Command::IO_SPACE | Command::MEMORY_SPACE);
+        if command_disable_decode != command_orig {
+            self.set_command(device_function, command_disable_decode);
+        }
+
         let bar_orig = self
             .configuration_access
             .read_word(device_function, BAR0_OFFSET + 4 * bar_index);
@@ -265,6 +272,10 @@ impl<C: ConfigurationAccess> PciRoot<C> {
             bar_orig,
         );
 
+        if command_disable_decode != command_orig {
+            self.set_command(device_function, command_orig);
+        }
+
         if bar_orig & 0x00000001 == 0x00000001 {
             // I/O space
             let address = bar_orig & 0xfffffffc;