Backport PCIe patches to 6.14. #6657
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This reverts commit d1f74f3.
…st-clk-ms"" This reverts commit 385ee6b.
This reverts commit 0f8b461.
…or downstream device"" This reverts commit 5d527cb.
About to add the upstream PCIe nodes, so remove the downstream ones to avoid duplicated nodes and build breakage. Signed-off-by: Dave Stevenson <[email protected]>
Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller. Signed-off-by: Stanimir Varbanov <[email protected]>
Update brcmstb PCIe controller bindings with bcm2712 compatible. Signed-off-by: Stanimir Varbanov <[email protected]>
Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) hardware block found in bcm2712. The interrupt controller is used to handle MSI-X interrupts from peripherials behind PCIe endpoints like RP1 south bridge found in RPi5. There are two MIPs on bcm2712, the first has 64 consecutive SPIs assigned to 64 output vectors, and the second has 17 SPIs, but only 8 of them are consecutive starting at the 8th output vector. Signed-off-by: Stanimir Varbanov <[email protected]>
Instead of copying fields from pcie_cfg_data structure to brcm_pcie reference it directly. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelil <[email protected]>
BCM2712 memory map can support up to 64GB of system memory, thus expand the inbound window size in calculation helper function. The change is save for the currently supported SoCs that has smaller inbound window sizes. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
Add bare minimum amount of changes in order to support PCIe RC hardware IP found on RPi5. The PCIe controller on bcm2712 is based on bcm7712 and as such it inherits register offsets, perst, bridge_reset ops and inbound windows count. Although, the implementation for bcm2712 needs a workaround related to the control of the bridge_reset where turning off of the root port must not shutdown the bridge_reset and this must be avoided. To implement this workaround a quirks field is introduced in pcie_cfg_data struct. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
The default input reference clock for the PHY PLL is 100Mhz, except for some devices where it is 54Mhz like bcm2712C1 and bcm2712D0. To implement this adjustments introduce a new .post_setup op in pcie_cfg_data and call it at the end of brcm_pcie_setup function. The bcm2712 .post_setup callback implements the required MDIO writes that switch the PLL refclk and also change PHY PM clock period. Without this RPi5 PCIex1 is unable to enumerate endpoint devices on the expansion connector. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
In case brcmstb PCIe driver and MIP MSI-X interrupt controller drivers are built as modules there could be a race in probing. To avoid this add a softdep to MIP driver to guarantee that MIP driver will be load first. Signed-off-by: Stanimir Varbanov <[email protected]>
A call to of_parse_phandle() increments refcount, of_node_put must be called when done the work on it. Fix missing of_node_put() on the msi_np device node by using scope based of_node_put() cleanups. Cc: [email protected] # v5.10+ Fixes: 40ca1bf ("PCI: brcmstb: Add MSI support") Signed-off-by: Stanimir Varbanov <[email protected]>
Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov <[email protected]>
Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov <[email protected]>
Make changes to the code that limits the PCIe max speed.
(1) Do the changes before link-up, not after. We do not want
to temporarily rise to a higher speed than desired.
(2) Use constants from pci_reg.h when possible
(3) Use uXX_replace_bits(...) for setting a register field.
(4) Use the internal link capabilities register for writing
the max speed, not the official config space register
where the speed field is RO. Updating this field is
not necessary to limit the speed so this mistake was
harmless.
Signed-off-by: Jim Quinlan <[email protected]>
If regulator_bulk_get() returns an error, no regulators are created and we need to set their number to zero. If we do not do this and the PCIe link-up fails, regulator_bulk_free() will be invoked and effect a panic. Also print out the error value, as we cannot return an error upwards as Linux will WARN on an error from add_bus(). Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]>
Our system for enabling and disabling regulators is designed to work only on the port driver below the root complex. The conditions to discriminate for this case should be the same when we are adding or removing the bus. Without this change the regulators may be disabled prematurely when a bus further down the tree is removed. Fixes: 9e6be01 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]>
The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SOC. One of the map_bus methods used these constants, the other used different constants. Fortunately there was no problem because the SoCs that used the latter map_bus method all had the same register constants. Remove the redundant constants and adjust the code to use them. In addition, update EXT_CFG_DATA to use the 4k-page based config space access system, which is what the second map_bus method was already using. Signed-off-by: Jim Quinlan <[email protected]>
The HW team has decided to "tighten" some field definitions in the MDIO packet format. Fortunately these two changes may be made in a backwards compatible manner. The CMD field used to be 12 bits and now is one. This change is backwards compatible because the field's starting bit position is unchanged and the only commands we've used have values 0 and 1. The PORT field's width has been changed from four to five bits. When written, the new bit is not contiguous with the other four. Fortunately, this change is backwards compatible because we have never used anything other than 0 for the port field's value. Signed-off-by: Jim Quinlan <[email protected]>
Just make it clear to the reader that there is a conversion happening, in this case from an int type to an irq_hw_number_t, an unsigned long int. Signed-off-by: Jim Quinlan <[email protected]>
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Things to test or add back in:
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Well volunteered. |
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If I add downstream patches to this PR, do you want them squashed to a single commit on top of the upstream backport, or separate? |
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I'm not fussed - it's a probably a utility vs effort trade-off. |
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Ideally we want all fixes upstreamed, so keeping them as individual patches that can be sent directly upstream would be the best bet. |
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This backports https://lore.kernel.org/linux-arm-kernel/[email protected]/ and https://lore.kernel.org/linux-arm-kernel/[email protected]/. The first should hit 6.15, the latter some time after.
I've had to revert the revert of "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device" to get these series to apply. Please re-review the handling of that one, and we ought to feed a fix back upstream if there is still an issue.
@P33M.