Done as part of E2.1 Digital Electronics II at Imperial College London alongside Omar Sharif, with thanks to the brilliant Prof. Peter Cheung. All required and optional challenges part of the lab complete.
The Altera Cyclone V SoC
Quick guide to each part:
Part 1: Schematic vs Verilog
- ex1 Schematic capture using Quartus – 7-Segment Display
- ex2 7-Segment decoder in Verilog HDL
- ex3 10-bit binary switch values on three 7-segment displays
- ex4 (optional) Displaying 10-bit binary as BCD digits on the 7-segment displays
Part 2: Counters & FSMs
- ex5 Designing a Counter
- ex6 Implementing a 16-bit counter on DE1
- ex7 Linear Feedback Shift Register (LFSR) and PRBS
- ex8 (optional) Starting line delay circuit
- ex9 (optional) A reaction meter
Part 3: DAC & Tone Generator
- ex10 Interface with the MCP4911 Digital-to-Analogue Converter
- ex11 D-to-A conversion using pulse-width modulation
- ex12 Designing and testing a sinewave table in ROM
- ex13 A fixed frequency sinewave generator
- ex14 (optional) A variable sinewave generator
- ex15 (optional) Using the A-to-D converter
Part 4: ADC/DAC & Echo Synthesizer
- ex16 An audio in-and-out (all pass) loop
- ex17 Echo Synthesizer with fixed delay
- ex18 Multiple echoes
- ex19 (optional) Echo Synthesizer with Variable delay
For more information, have a look at Prof. Peter Cheung's open-source experiment homepage, which can be found here.
For a walk-through of our work and thought process while building through these challenges, have a look at LabBook.pdf
... and as usual- if anything, the door is always open. Contact details in bio!
Enjoy :)