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WIP: realign to EFCL Summer School#430

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FrancescoConti wants to merge 27 commits intomasterpulp-platform/pulpissimo:masterfrom fc/synthpulp-platform/pulpissimo:fc/synthCopy head branch name to clipboard

+1,221-31

Commits

Commits on May 25, 2024

• Add zyboz7 FPGA port

  

  micprog

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• Make vsim compilation properly stop at errors + update runtime for CV32E40X

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• Add extremely preliminary FIR XIFU

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• Fix missing deps in manually hacked Bender.lock

  FrancescoConti

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• Update Bender.lock, Bender.yml, Xilinx constraints, memory size.

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• Fix Bender.lock

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• Use deps in GitHub only

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• Fix Bender.lock manually

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• Update Bender + update runtime + add minimal test for XIFU

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• Add symlinks to FIR HWPE & XIFU + CV32E40X + pulp_soc to deps folder

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• Update Bender.yml/lock with beautified pulp_soc

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• In this branch, use CORE_TYPE=3 (CV32E40X)

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• Update pulp_soc version

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• Fix pulp_soc

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• Fix defaults to CV32E40X in the right places

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• Adapt to LLVM-based setup + tracing in CV32E40X

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• Log all signals automatically in QuestaSim

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• Update versions + tests, working XIFU

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• remove ssh from Bender.lock and .yml

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• Realign Bender + sw submodules after rebase (to check)

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• Update pulp_soc

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Commits on May 31, 2024

• Fix potential (?) syntax error on some machines

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• Update fir-xifu (and pulp_soc)

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Commits on Jul 26, 2024

• Add synthesis dependencies

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• Improvements to ease non-free synthesis flow

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• point CI to LLVM (currently, EFCL Summer School version) in this branch

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Commits on Oct 25, 2024

• Add tiny entry in README + small fix to make checkout-synthesis rule

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