x411: fpga: enable QSFP28 experimental modes. They were not tested yet.

ptrkrysik · May 23, 2023 · e07a4b0 · e07a4b0
1 parent 22ee87b
commit e07a4b0
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Showing 3 changed files with 56 additions and 1 deletion.
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile
@@ -49,11 +49,13 @@ X410_X4_100:  DEFS += $(QSFP0_4X10GBE)                 RFBW_100M=1 DRAM_CH=4*$(D
 X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0
 X410_C1_100:  DEFS += $(QSFP0_100GBE)                  RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X410_C1_200:  DEFS += $(QSFP0_100GBE)                  RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
+X411_C1_200:  DEFS += $(QSFP0_100GBE)                  RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X410_X1_200:  DEFS += $(QSFP0_10GBE)                   RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X410_XG_200:  DEFS += $(QSFP0_10GBE)   $(QSFP1_10GBE)  RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X410_X4_200:  DEFS += $(QSFP0_4X10GBE)                 RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X411_X4_200:  DEFS += $(QSFP0_4X10GBE)                 RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
 X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
+X411_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
 X410_X1_400:  DEFS += $(QSFP0_10GBE)                   RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
 X410_XG_400:  DEFS += $(QSFP0_10GBE)   $(QSFP1_10GBE)  RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
 X410_X4_400:  DEFS += $(QSFP0_4X10GBE)                 RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
@@ -203,14 +205,22 @@ X410_C1_100: X410_IP build/usrp_x410_fpga_CG_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
 	$(call post_build,X410,CG_100)
 
-X410_C1_200: X410_IP build/usrp_x410_fpga_CG_200.dts
+X410_C1_200: X410_IP build/usrp_x410_fpga_C1_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,CG_200)
 
+X411_C1_200: X411_IP build/usrp_x411_fpga_C1_200.dts
+	$(call vivado_build,X411,$(DEFS) X411=1,$(X411_200_DEFAULTS))
+	$(call post_build,X411,CG_200)
+
 X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,X4C_200)
 
+X411_X4C_200: X411_IP build/usrp_x411_fpga_X4C_200.dts
+	$(call vivado_build,X411,$(DEFS) X411=1,$(X411_200_DEFAULTS))
+	$(call post_build,X411,X4C_200)
+
 ##
 ##Other Make Targets
 ##------------------

diff --git a/fpga/usrp3/top/x400/dts/usrp_x411_fpga_CG.dts b/fpga/usrp3/top/x400/dts/usrp_x411_fpga_CG.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ * Copyright 2023 Piotr Krysik <[email protected]>
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x411-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-100gbe-port0.dtsi"
+
+#include "x410-100gbe-port1.dtsi"
diff --git a/fpga/usrp3/top/x400/dts/usrp_x411_fpga_X4C.dts b/fpga/usrp3/top/x400/dts/usrp_x411_fpga_X4C.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2021 Ettus Research, a National Instruments Brand
+ *
+ * SPDX-License-Identifier: LGPL-3.0-or-later
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "x410-version-info.dtsi"
+
+#include "x411-fpga.dtsi"
+
+#include "x410-common.dtsi"
+
+#include "x410-rfdc.dtsi"
+
+#include "x410-dma.dtsi"
+
+#include "x410-10gbe-port0-x4.dtsi"
+
+#include "x410-100gbe-port1.dtsi"