GitHub - philippefaes/VHDL-hierarchy-demo

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
.settings		.settings
.project		.project
README		README
a.vhd		a.vhd
a_rtl1.vhd		a_rtl1.vhd
a_rtl2.vhd		a_rtl2.vhd
b.vhd		b.vhd
b_rtl1.vhd		b_rtl1.vhd
b_rtl2.vhd		b_rtl2.vhd
c.vhd		c.vhd
c_rtl1.vhd		c_rtl1.vhd
c_rtl2.vhd		c_rtl2.vhd
top_components.vhd		top_components.vhd
top_configuration.vhd		top_configuration.vhd
top_direct.vhd		top_direct.vhd
top_direct_with_generics.vhd		top_direct_with_generics.vhd

Repository files navigation

This project demonstrates three ways of how to configure a VHDL chip structure:

1. Adapt the build scripts
2. Direct instantitation with generates
3. Configurations

This project can easily be imported in the free Sigasi Starter Edition: 
http://www.sigasi.com/sigasi-starter-edition