Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Issue #82 #83

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

Issue #82 #83

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
07220fe
Modified to fix crash during PAR in ISE 14.7 in some instances.
jvm3487 Dec 18, 2014
dc3a61f
Update dvi_gen_top.v
jvm3487 Dec 18, 2014
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion systems/atlys/data/atlys.ucf
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -350,7 +350,7 @@ TIMESPEC TS_tck_to_wb_clk = FROM "tck_pad_i" TO "wb_clk" TIG;
TIMESPEC TS_wb_to_tck_clk = FROM "wb_clk" TO "tck_pad_i" TIG;

# HDMI constraints
NET "dvi_gen0/clk50m_bufg" TNM_NET = "TNM_CLK50M";
NET "dvi_clk" TNM_NET = "TNM_CLK50M";
TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;

NET "pclk" TNM_NET = "TNM_PCLK";
Expand Down
4 changes: 1 addition & 3 deletions systems/atlys/rtl/verilog/clkgen.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -162,14 +162,12 @@ BUFG dcm0_clkfx_bufg
.I (dcm0_clkfx_prebufg)
);

/* This is buffered in dvi_gen
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg)
);
*/

BUFG pll0_clk1_bufg
(// Outputs
Expand All @@ -184,7 +182,7 @@ assign sync_ddr2_rst_n = dcm0_locked;
assign ddr2_if_clk_o = dcm0_clkfx; // 266MHz
assign clk100_o = dcm0_clk0; // 100MHz

assign dvi_clk_o = dcm0_clkdv_prebufg;
assign dvi_clk_o = dcm0_clkdv;

//
// Reset generation
Expand Down
8 changes: 4 additions & 4 deletions systems/atlys/rtl/verilog/dvi_gen/dvi_gen_top.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -71,12 +71,12 @@ module dvi_gen_top (
wire locked;
wire reset;

wire clk50m, clk50m_bufg;
wire /*clk50m,*/ clk50m_bufg;

wire pwrup;

assign clk50m = dvi_clk_i;
BUFG clk50m_bufgbufg (.I(clk50m), .O(clk50m_bufg));
assign clk50m_bufg = dvi_clk_i;
/*BUFG clk50m_bufgbufg (.I(clk50m), .O(clk50m_bufg));*/

wire pclk_lckd;
wire RSTBTN;
Expand Down Expand Up @@ -433,7 +433,7 @@ module dvi_gen_top (
.LOCKED(pclk_lckd),
.PROGDONE(progdone),
.STATUS(),
.CLKIN(clk50m),
.CLKIN(clk50m_bufg),
.FREEZEDCM(1'b0),
.PROGCLK(clk50m_bufg),
.PROGDATA(progdata),
Expand Down