Support for Altera DE2 board added

README.md

@@ -1,4 +1,5 @@
 orpsoc-cores
 ============
 
-Core description files for ORPSoCv3
+Core description files for ORPSoCv3.
+Support for Altera DE2 board added (alpha, written by Tran Cong Nam).

cores/elf-loader/vpi_wrapper.c

@@ -1,3 +1,5 @@
+#include <stdlib.h>
+#include <ctype.h>
 #include <vpi_user.h>
 #include "elf-loader.h"
 

systems/de2/data/de2.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

systems/de2/data/options.tcl

@@ -0,0 +1,17 @@
+# See Cyclone II FPGA Family Errata, needed for ddual-port dual-clock mode M4K
+# (http://www.altera.com/support/kdb/solutions/fb27180.html)
+
+set_parameter -name CYCLONEII_SAFE_WRITE  "VERIFIED_SAFE"
+
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS_INPUT_TRI_STATED"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+# Make it pass STA
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

systems/de2/data/pinmap.tcl

@@ -0,0 +1,208 @@
+# Clock / Reset
+
+set_location_assignment PIN_G26 -to rst_n_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i
+set_location_assignment PIN_N2 -to sys_clk_pad_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i
+
+# SD card
+#set_location_assignment PIN_V20 -to sd_clk_pad_o
+
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_clk_pad_o
+#set_location_assignment PIN_Y20 -to sd_cmd_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_cmd_pad_o
+#set_location_assignment PIN_W20 -to sd_dat_pad_i
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat_pad_i
+#set_location_assignment PIN_U20 -to sd_dat3_pad_o
+#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat3_pad_o
+
+# UART
+set_location_assignment PIN_C25 -to uart0_srx_pad_i
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i
+set_location_assignment PIN_B25 -to uart0_stx_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o
+
+# SDRAM
+set_location_assignment PIN_T6 -to sdram_a_pad_o[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0]
+set_location_assignment PIN_V4 -to sdram_a_pad_o[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1]
+set_location_assignment PIN_V3 -to sdram_a_pad_o[2]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2]
+set_location_assignment PIN_W2 -to sdram_a_pad_o[3]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3]
+set_location_assignment PIN_W1 -to sdram_a_pad_o[4]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4]
+set_location_assignment PIN_U6 -to sdram_a_pad_o[5]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5]
+set_location_assignment PIN_U7 -to sdram_a_pad_o[6]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6]
+set_location_assignment PIN_U5 -to sdram_a_pad_o[7]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7]
+set_location_assignment PIN_W4 -to sdram_a_pad_o[8]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8]
+set_location_assignment PIN_W3 -to sdram_a_pad_o[9]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9]
+set_location_assignment PIN_Y1 -to sdram_a_pad_o[10]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10]
+set_location_assignment PIN_V5 -to sdram_a_pad_o[11]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11]
+
+set_location_assignment PIN_V6 -to sdram_dq_pad_io[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0]
+set_location_assignment PIN_AA2 -to sdram_dq_pad_io[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1]
+set_location_assignment PIN_AA1 -to sdram_dq_pad_io[2]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2]
+set_location_assignment PIN_Y3 -to sdram_dq_pad_io[3]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3]
+set_location_assignment PIN_Y4 -to sdram_dq_pad_io[4]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4]
+set_location_assignment PIN_R8 -to sdram_dq_pad_io[5]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5]
+set_location_assignment PIN_T8 -to sdram_dq_pad_io[6]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6]
+set_location_assignment PIN_V7 -to sdram_dq_pad_io[7]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7]
+set_location_assignment PIN_W6 -to sdram_dq_pad_io[8]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8]
+set_location_assignment PIN_AB2 -to sdram_dq_pad_io[9]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9]
+set_location_assignment PIN_AB1 -to sdram_dq_pad_io[10]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10]
+set_location_assignment PIN_AA4 -to sdram_dq_pad_io[11]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11]
+set_location_assignment PIN_AA3 -to sdram_dq_pad_io[12]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12]
+set_location_assignment PIN_AC2 -to sdram_dq_pad_io[13]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13]
+set_location_assignment PIN_AC1 -to sdram_dq_pad_io[14]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14]
+set_location_assignment PIN_AA5 -to sdram_dq_pad_io[15]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15]
+
+set_location_assignment PIN_AD2 -to sdram_dqm_pad_o[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0]
+set_location_assignment PIN_Y5 -to sdram_dqm_pad_o[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1]
+
+set_location_assignment PIN_AE2 -to sdram_ba_pad_o[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0]
+set_location_assignment PIN_AE3 -to sdram_ba_pad_o[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1]
+
+set_location_assignment PIN_AB3 -to sdram_cas_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o
+
+set_location_assignment PIN_AA6 -to sdram_cke_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o
+
+set_location_assignment PIN_AC3 -to sdram_cs_n_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o
+
+set_location_assignment PIN_AB4 -to sdram_ras_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o
+
+set_location_assignment PIN_AD3 -to sdram_we_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o
+
+set_location_assignment PIN_AA7 -to sdram_clk_pad_o
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o
+
+# RED LED
+set_location_assignment PIN_AE23 -to led_r_pad_o[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[0]
+set_location_assignment PIN_AF23 -to led_r_pad_o[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[1]
+set_location_assignment PIN_AB21 -to led_r_pad_o[2]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[2]
+set_location_assignment PIN_AC22 -to led_r_pad_o[3]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[3]
+set_location_assignment PIN_AD22 -to led_r_pad_o[4]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[4]
+set_location_assignment PIN_AD23 -to led_r_pad_o[5]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[5]
+set_location_assignment PIN_AD21 -to led_r_pad_o[6]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[6]
+set_location_assignment PIN_AC21 -to led_r_pad_o[7]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[7]
+set_location_assignment PIN_AA14 -to led_r_pad_o[8]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[8]
+set_location_assignment PIN_Y13 -to led_r_pad_o[9]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[9]
+
+# GREEN LED
+set_location_assignment PIN_AE22 -to gpio0_io[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0]
+set_location_assignment PIN_AF22 -to gpio0_io[1]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1]
+set_location_assignment PIN_W19 -to gpio0_io[2]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2]
+set_location_assignment PIN_V18 -to gpio0_io[3]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3]
+set_location_assignment PIN_U18 -to gpio0_io[4]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4]
+set_location_assignment PIN_U17 -to gpio0_io[5]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5]
+set_location_assignment PIN_AA20 -to gpio0_io[6]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6]
+set_location_assignment PIN_Y18 -to gpio0_io[7]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7]

systems/de2/data/wb_intercon.conf

@@ -0,0 +1,43 @@
+; or1k instruction bus master
+[master or1k_i]
+slaves =
+ sdram_ibus
+ rom0
+
+; or1k data bus master
+[master or1k_d]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+; debug master
+[master dbg]
+slaves =
+ sdram_dbus
+ uart0
+ gpio0
+
+[slave uart0]
+datawidth=8
+offset=0x90000000
+size=32
+
+[slave gpio0]
+datawidth=8
+offset=0x91000000
+size=2
+
+[slave rom0]
+offset=0xf0000100
+size=64
+
+; SDRAM
+; Have several ports with buffering features,
+; so we split each port into a seperate slave
+[slave sdram_dbus]
+offset=0
+size=0x2000000 ; 32MB
+[slave sdram_ibus]
+offset=0
+size=0x2000000 ; 32MB

systems/generic/generic.core → systems/de2/de2.core

@@ -1,16 +1,20 @@
 CAPI=1
 [main]
-depend = 
- adv_debug_sys
- dbg
+depend =
  jtag_tap
- jtag_vpi
+ wb_intercon
+ adv_debug_sys
  or1200
- elf-loader
- ram_wb
  uart16550
+ elf-loader
  vlog_tb_utils
- wb_utils
+ jtag_vpi
+ wiredelay
+ wb_sdram_ctrl
+ mor1kx
+ mt48lc16m16a2
+ gpio
+ altera_virtual_jtag
 
 simulators =
  icarus
@@ -19,16 +23,22 @@ simulators =
 [verilog]
 src_files = 
  rtl/verilog/clkgen.v
- rtl/verilog/intgen.v
- rtl/verilog/rom.v
  rtl/verilog/orpsoc_top.v
+ backend/rtl/verilog/pll.v
+ rtl/verilog/rom.v
+ rtl/verilog/wb_intercon.v
+
+
 include_files =
  rtl/verilog/include/or1200_defines.v
  rtl/verilog/include/orpsoc-defines.v
- rtl/verilog/include/orpsoc-params.v
  rtl/verilog/include/timescale.v
  rtl/verilog/include/uart_defines.v
+ rtl/verilog/wb_intercon.vh
+
+[icarus]
+iverilog_options = -DICARUS_SIM -DSIM
 
-tb_src_files = 
- bench/uart_decoder.v
- bench/orpsoc_tb.v
+[modelsim]
+vlog_options = +define+SIM +define+MODELSIM_SIM
+vsim_options = -L altera_mf_ver -L altera_mf

systems/de2/de2.core~origin_master

@@ -0,0 +1,44 @@
+CAPI=1
+[main]
+depend =
+ jtag_tap
+ wb_intercon
+ adv_debug_sys
+ or1200
+ uart16550
+ or1k-elf-loader
+ vlog_tb_utils
+ jtag_vpi
+ wiredelay
+ wb_sdram_ctrl
+ mor1kx
+ mt48lc16m16a2
+ gpio
+ altera_virtual_jtag
+
+simulators =
+ icarus
+ modelsim
+
+[verilog]
+src_files = 
+ rtl/verilog/clkgen.v
+ rtl/verilog/orpsoc_top.v
+ backend/rtl/verilog/pll.v
+ rtl/verilog/rom.v
+ rtl/verilog/wb_intercon.v
+
+
+include_files =
+ rtl/verilog/include/or1200_defines.v
+ rtl/verilog/include/orpsoc-defines.v
+ rtl/verilog/include/timescale.v
+ rtl/verilog/include/uart_defines.v
+ rtl/verilog/wb_intercon.vh
+
+[icarus]
+iverilog_options = -DICARUS_SIM -DSIM
+
+[modelsim]
+vlog_options = +define+SIM +define+MODELSIM_SIM
+vsim_options = -L altera_mf_ver -L altera_mf