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RISC-V: Add Zcmp cm.mv instructions testcases.
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pz9115 authored and Mary Bennett committed Oct 2, 2023
1 parent d0680f9 commit 25ea490
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24 changes: 24 additions & 0 deletions gas/testsuite/gas/riscv/zc-test-no-zcmp.d
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#as: -march=rv64i_zca
#source: zc-zcmp-mv-mix.s
#objdump: -dr

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s6,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s2
0+006 <L2>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s2
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a2
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s4
22 changes: 22 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mv-mix.d
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#as: -march=rv64i_zca_zcmp
#source: zc-zcmp-mv-mix.s
#objdump: -dr

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s6,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s2
0+006 <L2>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+adea[ ]+cm.mva01s[ ]+s3,s2
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s3
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a2
[ ]*[0-9a-f]+:[ ]+ae6e[ ]+cm.mva01s[ ]+s4,s3
16 changes: 16 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mv-mix.s
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target:
mv a0, s1
mv s6, a1
mv a0, s2
L2:
mv s3, a1
mv a0, s3
mv s3, a1
# merge
mv a0, s3
mv a1, s2
mv a0, s3
mv s3, a1
mv s3, a2
mv a1, s3
mv a0, s4
22 changes: 22 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mva01s.d
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#as: -march=rv64i_zca_zcmp
#source: zc-zcmp-mva01s.s
#objdump: -dr

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1
[ ]*[0-9a-f]+:[ ]+acea[ ]+cm.mva01s[ ]+s1,s2
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s8
[ ]*[0-9a-f]+:[ ]+adfe[ ]+cm.mva01s[ ]+s3,s7
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s1
0+00c <L2>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a1,s3
[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+a0,s4
[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7
[ ]*[0-9a-f]+:[ ]+affe[ ]+cm.mva01s[ ]+s7,s7
19 changes: 19 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mva01s.s
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target:
mv a0, s1 # dst registers should be one a0 and one a1
# merge
mv a0, s1
mv a1, s2
mv a0, s1
mv a0, s8 # s0 is out of range
# merge
mv a1, s7
mv a0, s3
mv a0, s1 # can't merge across label.
L2:
mv a1, s3
cm.mva01s s0, s7
mv a0, s4
cm.mva01s s0, s7
# merge
mv a1, s7
mv a0, s7
3 changes: 3 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.d
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#as: -march=rv64i_zca_zcmp
#source: zc-zcmp-mvsa01-fail.s
#error_output: zc-zcmp-mvsa01-fail.l
7 changes: 7 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.l
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.*: Assembler messages:
.*: Error: illegal operands `cm.mvsa01 s0,s0'
.*: Error: illegal operands `cm.mvsa01 s1,s1'
.*: Error: illegal operands `cm.mvsa01 s7,s7'
.*: Error: illegal operands `cm.mvsa01 s0,s8'
.*: Error: illegal operands `cm.mvsa01 s8,s0'
.*: Error: illegal operands `cm.mvsa01 s0,a0'
10 changes: 10 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mvsa01-fail.s
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target:
# sreg1 != sreg2
cm.mvsa01 s0,s0
cm.mvsa01 s1,s1
cm.mvsa01 s7,s7

# invalid range
cm.mvsa01 s0,s8
cm.mvsa01 s8,s0
cm.mvsa01 s0,a0
24 changes: 24 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mvsa01.d
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#as: -march=rv64i_zca_zcmp
#source: zc-zcmp-mvsa01.s
#objdump: -dr

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s2,a0
[ ]*[0-9a-f]+:[ ]+acaa[ ]+cm.mvsa01[ ]+s1,s2
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s8,a0
[ ]*[0-9a-f]+:[ ]+adbe[ ]+cm.mvsa01[ ]+s3,s7
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s1,a0
0+00e <L2>:
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s3,a1
[ ]*[0-9a-f]+:[ ]+ac3e[ ]+cm.mvsa01[ ]+s0,s7
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s4,a0
[ ]*[0-9a-f]+:[ ]+ac3e[ ]+cm.mvsa01[ ]+s0,s7
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s7,a1
[ ]*[0-9a-f]+:[ ]+.*[ ]+mv[ ]+s7,a0
19 changes: 19 additions & 0 deletions gas/testsuite/gas/riscv/zc-zcmp-mvsa01.s
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@@ -0,0 +1,19 @@
target:
mv s1, a0 # src registers should be one a0 and one a1
mv s2, a0
# merge
mv s1, a0
mv s2, a1
mv s1, a0
mv s8, a0 # s0 is out of range
# merge
mv s7, a1
mv s3, a0
mv s1, a0 # can't merge across label.
L2:
mv s3, a1
cm.mvsa01 s0, s7
mv s4, a0
cm.mvsa01 s0, s7
mv s7, a1 # dst can't be the same
mv s7, a0

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