Bit Manipulation Instructions in GNU Assembler

	Bit manipulation instructions are useful to work on single
	bits or groups of bits within a word. The cv.bitrev instruction
	from a bit manipulation perspective without describing it’s
	application as part of an FFT. The bit reverse instruction
	will reverse bits in groupings of 1, 2 or 3 bits.

	bfd/
            * elfxx-riscv.c: Added INSN_CLASS_COREV_BITMANIP.
	gas/config/
            * tc-riscv.c: Added b6 for ENCODE_CV_BITMANIP_UIMM5
              for unsigned 5-bit immediate and b7 for
              ENCODE_CV_BITMANIP_UIMM2 for unsigned 2-bit immediate.
	gas/doc/
            * c-riscv.texi: Updated documentation to include
              COREV bit manipulation version 1 and 2.
	include/opcode/
            * riscv-opc.h: Added corresponding 16 MATCH and MASK
              macros for bit manipulation.
            * riscv.h: Added EXTRACT_CV_BITMANIP_UIMM5
              EXTRACT_CV_BITMANIP_UIMM2, ENCODE_CV_BITMANIP_UIMM5,
              ENCODE_CV_BITMANIP_UIMM2.
	opcodes/
            * riscv-dis.c: Added disassemble information for
              EXTRACT_CV_BITMANIP_UIMM5 and EXTRACT_CV_BITMANIP_UIMM2.
            * riscv-opc.c: Added 16 instructions to riscv_opcode[].

Signed-off-by: NandniJamnadas <[email protected]>

Changed the immediate order in bit maipulation instructions

Resolves the encoding problem identified in #68.

Files Changed:

gas/testsuite/gas/riscv:
 * cv-bitmanip-march-xcorev.d: Updated the tests with the changed
   immediate order.
cv-bitmanip-march-xcorev.s: Likewise.
cv-bitmanip-march-xcorevbitmanip.d: Likewise.
cv-bitmanip-march-xcorevbitmanip.s: Likewise.
cv-bitrev-fail.l: Likewise.
cv-bitrev-fail.s: Likewise.
cv-bitrev-pass.d: Likewise.
cv-bitrev-pass.s: Likewise.

opcodes:
 * riscv-opc.c: Changed the order of ls2 and ls3 in instructions
   cv.extract, cv.instert, cv.bclr, cv.bset, and cv.bitrev.

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+    "C_Cpp.dimInactiveRegions": false
+}

bfd/elfxx-riscv.c

@@ -1396,6 +1396,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xcvbi",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvelw",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvsimd",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvbitmanip",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2608,6 +2609,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvelw");
     case INSN_CLASS_XCVSIMD:
       return riscv_subset_supports (rps, "xcvsimd");
+    case INSN_CLASS_XCVBITMANIP:
+      return riscv_subset_supports (rps, "xcvbitmanip");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2862,6 +2865,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvelw";
     case INSN_CLASS_XCVSIMD:
       return "xcvsimd";
+    case INSN_CLASS_XCVBITMANIP:
+      return "xcvbitmanip";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:

gas/config/tc-riscv.c

@@ -1395,6 +1395,16 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      used_bits |= ENCODE_CV_SIMD_IMM6(-1U);
 	      ++oparg; break;
 	    }
+	  else if (oparg[1] == '6')
+	    {
+	      used_bits |= ENCODE_CV_BITMANIP_UIMM5(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '7')
+	    {
+	      used_bits |= ENCODE_CV_BITMANIP_UIMM2(-1U);
+	      ++oparg; break;
+	    }
 	  else if (oparg[1] == '8')
 	    {
 	      used_bits |= ENCODE_CV_SIMD_UIMM6(-1U);
@@ -3447,6 +3457,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  ip->insn_opcode |= ENCODE_CV_SIMD_IMM6 (imm_expr->X_add_number);
 		  ++oparg;
 		}
+	      else if (oparg[1] == '6')
+		// b6: Luimm5 bits unsigned immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<0 || imm_expr->X_add_number>31) break;
+		  ip->insn_opcode |= ENCODE_CV_BITMANIP_UIMM5 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '7')
+		// b7: Luimm2 bits unsigned immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<0 || imm_expr->X_add_number>3) break;
+		  ip->insn_opcode |= ENCODE_CV_BITMANIP_UIMM2 (imm_expr->X_add_number);
+		  ++oparg;
+		}
 	      else if (oparg[1] == '8')
 		// b8: uimm6 bits unsigned immediate bits
 		{

gas/doc/c-riscv.texi

@@ -780,6 +780,11 @@ The Xcvsimd extension provides instructions for SIMD operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvbitmanip
+The Xcvbitmanip extension provides instructions for bitmanip operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 

gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bclr-fail.s
+#error_output: cv-bitmanip-bclr-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.l

@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bclr x32,x32,20,20'
+.*: Error: illegal operands `cv.bclr x33,x33,20,20'
+.*: Error: illegal operands `cv.bclr x6,x7,0,32'
+.*: Error: illegal operands `cv.bclr x6,x7,32,0'
+.*: Error: illegal operands `cv.bclr x6,x7,0,-1'
+.*: Error: illegal operands `cv.bclr x6,x7,-1,0'

gas/testsuite/gas/riscv/cv-bitmanip-bclr-fail.s

@@ -0,0 +1,9 @@
+target: 
+    #Register Tests
+    cv.bclr x32, x32, 20, 20
+    cv.bclr x33, x33, 20, 20
+    #Immediate Values Test
+    cv.bclr x6, x7, 0, 32
+    cv.bclr x6, x7, 32, 0
+    cv.bclr x6, x7, 0, -1
+    cv.bclr x6, x7, -1, 0

gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.d

@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bclr-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+
+   0:	2940105b          	cv.bclr	zero,zero,20,20
+   4:	294090db          	cv.bclr	ra,ra,20,20
+   8:	2941115b          	cv.bclr	sp,sp,20,20
+   c:	2944145b          	cv.bclr	s0,s0,20,20
+  10:	294a1a5b          	cv.bclr	s4,s4,20,20
+  14:	294f9fdb          	cv.bclr	t6,t6,20,20
+  18:	0003935b          	cv.bclr	t1,t2,0,0
+  1c:	3ff3935b          	cv.bclr	t1,t2,31,31

gas/testsuite/gas/riscv/cv-bitmanip-bclr-pass.s

@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.bclr x0, x0, 20, 20
+    cv.bclr x1, x1, 20, 20
+    cv.bclr x2, x2, 20, 20
+    cv.bclr x8, x8, 20, 20
+    cv.bclr x20, x20, 20, 20
+    cv.bclr x31, x31, 20, 20
+    #Immediate Values Test
+    cv.bclr x6, x7, 0, 0
+    cv.bclr x6, x7, 31, 31

gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bclrr-fail.s
+#error_output: cv-bitmanip-bclrr-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bclrr x32,x32,x32'
+.*: Error: illegal operands `cv.bclrr x33,x33,x33'

gas/testsuite/gas/riscv/cv-bitmanip-bclrr-fail.s

@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.bclrr x32, x32, x32
+    cv.bclrr x33, x33, x33

gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.d

@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bclrr-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800302b          	cv.bclrr	zero,zero,zero
+   4:	3810b0ab          	cv.bclrr	ra,ra,ra
+   8:	3821312b          	cv.bclrr	sp,sp,sp
+   c:	3884342b          	cv.bclrr	s0,s0,s0
+  10:	394a3a2b          	cv.bclrr	s4,s4,s4
+  14:	39ffbfab          	cv.bclrr	t6,t6,t6

gas/testsuite/gas/riscv/cv-bitmanip-bclrr-pass.s

@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.bclrr x0, x0, x0
+    cv.bclrr x1, x1, x1
+    cv.bclrr x2, x2, x2
+    cv.bclrr x8, x8, x8
+    cv.bclrr x20, x20, x20
+    cv.bclrr x31, x31, x31

gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bitrev-fail.s
+#error_output: cv-bitmanip-bitrev-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.l

@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bitrev x32,x32,2,20'
+.*: Error: illegal operands `cv.bitrev x33,x33,2,20'
+.*: Error: illegal operands `cv.bitrev x6,x7,-1,0'
+.*: Error: illegal operands `cv.bitrev x6,x7,0,-1'
+.*: Error: illegal operands `cv.bitrev x6,x7,0,32'
+.*: Error: illegal operands `cv.bitrev x6,x7,4,0'

gas/testsuite/gas/riscv/cv-bitmanip-bitrev-fail.s

@@ -0,0 +1,9 @@
+target:
+    #Register Tests
+    cv.bitrev x32, x32, 2, 20
+    cv.bitrev x33, x33, 2, 20
+    #Immediate Values Test
+    cv.bitrev x6, x7, -1, 0
+    cv.bitrev x6, x7, 0, -1
+    cv.bitrev x6, x7, 0, 32
+    cv.bitrev x6, x7, 4, 0

gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.d

@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bitrev-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c540105b          	cv.bitrev	zero,zero,2,20
+   4:	c54090db          	cv.bitrev	ra,ra,2,20
+   8:	c541115b          	cv.bitrev	sp,sp,2,20
+   c:	c544145b          	cv.bitrev	s0,s0,2,20
+  10:	c54a1a5b          	cv.bitrev	s4,s4,2,20
+  14:	c54f9fdb          	cv.bitrev	t6,t6,2,20
+  18:	c003935b          	cv.bitrev	t1,t2,0,0
+  1c:	c7f3935b          	cv.bitrev	t1,t2,3,31

gas/testsuite/gas/riscv/cv-bitmanip-bitrev-pass.s

@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.bitrev x0, x0, 2, 20
+    cv.bitrev x1, x1, 2, 20
+    cv.bitrev x2, x2, 2, 20
+    cv.bitrev x8, x8, 2, 20
+    cv.bitrev x20, x20, 2, 20
+    cv.bitrev x31, x31, 2, 20
+    #Immediate Values Test
+    cv.bitrev x6, x7, 0, 0
+    cv.bitrev x6, x7, 3, 31

gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bset-fail.s
+#error_output: cv-bitmanip-bset-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.l

@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bset x32,x32,20,20'
+.*: Error: illegal operands `cv.bset x33,x33,20,20'
+.*: Error: illegal operands `cv.bset x6,x7,0,32'
+.*: Error: illegal operands `cv.bset x6,x7,32,0'
+.*: Error: illegal operands `cv.bset x6,x7,0,-1'
+.*: Error: illegal operands `cv.bset x6,x7,-1,0'

gas/testsuite/gas/riscv/cv-bitmanip-bset-fail.s

@@ -0,0 +1,9 @@
+target: 
+    #Register Tests
+    cv.bset x32, x32, 20, 20
+    cv.bset x33, x33, 20, 20
+    #Immediate Values Test
+    cv.bset x6, x7, 0, 32
+    cv.bset x6, x7, 32, 0
+    cv.bset x6, x7, 0, -1
+    cv.bset x6, x7, -1, 0

gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.d

@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bset-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+
+   0:	6940105b          	cv.bset	zero,zero,20,20
+   4:	694090db          	cv.bset	ra,ra,20,20
+   8:	6941115b          	cv.bset	sp,sp,20,20
+   c:	6944145b          	cv.bset	s0,s0,20,20
+  10:	694a1a5b          	cv.bset	s4,s4,20,20
+  14:	694f9fdb          	cv.bset	t6,t6,20,20
+  18:	4003935b          	cv.bset	t1,t2,0,0
+  1c:	7ff3935b          	cv.bset	t1,t2,31,31

gas/testsuite/gas/riscv/cv-bitmanip-bset-pass.s

@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.bset x0, x0, 20, 20
+    cv.bset x1, x1, 20, 20
+    cv.bset x2, x2, 20, 20
+    cv.bset x8, x8, 20, 20
+    cv.bset x20, x20, 20, 20
+    cv.bset x31, x31, 20, 20
+    #Immediate Values Test
+    cv.bset x6, x7, 0, 0
+    cv.bset x6, x7, 31, 31

gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bsetr-fail.s
+#error_output: cv-bitmanip-bsetr-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.bsetr x32,x32,x32'
+.*: Error: illegal operands `cv.bsetr x33,x33,x33'

gas/testsuite/gas/riscv/cv-bitmanip-bsetr-fail.s

@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.bsetr x32, x32, x32
+    cv.bsetr x33, x33, x33

gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.d

@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-bsetr-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3a00302b          	cv.bsetr	zero,zero,zero
+   4:	3a10b0ab          	cv.bsetr	ra,ra,ra
+   8:	3a21312b          	cv.bsetr	sp,sp,sp
+   c:	3a84342b          	cv.bsetr	s0,s0,s0
+  10:	3b4a3a2b          	cv.bsetr	s4,s4,s4
+  14:	3bffbfab          	cv.bsetr	t6,t6,t6

gas/testsuite/gas/riscv/cv-bitmanip-bsetr-pass.s

@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.bsetr x0, x0, x0
+    cv.bsetr x1, x1, x1
+    cv.bsetr x2, x2, x2
+    cv.bsetr x8, x8, x8
+    cv.bsetr x20, x20, x20
+    cv.bsetr x31, x31, x31

gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-clb-fail.s
+#error_output: cv-bitmanip-clb-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.clb x32,x32'
+.*: Error: illegal operands `cv.clb x33,x33'

gas/testsuite/gas/riscv/cv-bitmanip-clb-fail.s

@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.clb x32, x32
+    cv.clb x33, x33

gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.d

@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-clb-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4600302b          	cv.clb	zero,zero
+   4:	4600b0ab          	cv.clb	ra,ra
+   8:	4601312b          	cv.clb	sp,sp
+   c:	4604342b          	cv.clb	s0,s0
+  10:	460a3a2b          	cv.clb	s4,s4
+  14:	460fbfab          	cv.clb	t6,t6

gas/testsuite/gas/riscv/cv-bitmanip-clb-pass.s

@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.clb x0, x0
+    cv.clb x1, x1
+    cv.clb x2, x2
+    cv.clb x8, x8
+    cv.clb x20, x20
+    cv.clb x31, x31

gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-cnt-fail.s
+#error_output: cv-bitmanip-cnt-fail.l

gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.l

@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cnt x32,x32'
+.*: Error: illegal operands `cv.cnt x33,x33'

gas/testsuite/gas/riscv/cv-bitmanip-cnt-fail.s

@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cnt x32, x32
+    cv.cnt x33, x33

gas/testsuite/gas/riscv/cv-bitmanip-cnt-pass.d

@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvbitmanip
+#source: cv-bitmanip-cnt-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800302b          	cv.cnt	zero,zero
+   4:	4800b0ab          	cv.cnt	ra,ra
+   8:	4801312b          	cv.cnt	sp,sp
+   c:	4804342b          	cv.cnt	s0,s0
+  10:	480a3a2b          	cv.cnt	s4,s4
+  14:	480fbfab          	cv.cnt	t6,t6