Merge pull request #11 from mrLSD/rv-extension-A-test

RV32/64A extension tests

DecodeA.fs

@@ -40,17 +40,17 @@ let Decode (instr: InstrField) : InstructionA =
     match (opcode) with
     | 0b0101111 when funct3 = 0b010 ->
         match funct7 with
-        | 00010 -> LR_W      {| rd = rd; rs1 = rs1; aq = aq; rl = rl |}
-        | 00011 -> SC_W      {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}  
-        | 00001 -> AMOSWAP_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 00000 -> AMOADD_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} 
-        | 00100 -> AMOXOR_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 01100 -> AMOAND_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 01000 -> AMOOR_W   {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 10000 -> AMOMIN_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 10100 -> AMOMAX_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 11000 -> AMOMINU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
-        | 11100 -> AMOMAXU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b00010 -> LR_W      {| rd = rd; rs1 = rs1; aq = aq; rl = rl |}
+        | 0b00011 -> SC_W      {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}  
+        | 0b00001 -> AMOSWAP_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b00000 -> AMOADD_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |} 
+        | 0b00100 -> AMOXOR_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b01100 -> AMOAND_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b01000 -> AMOOR_W   {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b10000 -> AMOMIN_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b10100 -> AMOMAX_W  {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b11000 -> AMOMINU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
+        | 0b11100 -> AMOMAXU_W {| rd = rd; rs1 = rs1; rs2 = rs2; aq = aq; rl = rl |}
         | _ -> None
 
     | _ -> None

ExecuteA.fs

@@ -53,7 +53,7 @@ let execAMOADD_W (rd : Register) (rs1 : Register) (rs2 : Register) (mstate : Mac
     let memResult = loadWord mstate.Memory addr
     if memResult.IsNone then
         mstate.setRunState (Trap (MemAddress addr))
-    else        
+    else
         let resMemOp = (int64 memResult.Value) + rs2Val
         let mstate = mstate.storeMemoryWord addr resMemOp
         let mstate = mstate.setRegister rd (int64 memResult.Value)

ExecuteI.fs

@@ -197,7 +197,7 @@ let execSH (rs1 : Register) (rs2 : Register) (imm12 : InstrField) (mstate : Mach
 let execSW (rs1 : Register) (rs2 : Register) (imm12 : InstrField) (mstate : MachineState) =
     let addr = (mstate.getRegister rs1) + int64 imm12
     let rs2Val = mstate.getRegister rs2
-    let mstate = mstate.storeMemoryWord addr rs2Val 
+    let mstate = mstate.storeMemoryWord addr rs2Val
     mstate.incPC
 
 //=================================================

Tests/Tests.fsproj

@@ -37,6 +37,8 @@
       <Compile Include="rv32m\alu.fs" />
       <Compile Include="rv64m\alu.fs" />
 
+      <Compile Include="rv64a\amo.fs" />
+
       <Compile Include="Program.fs" />
     </ItemGroup>
 

Tests/asm/Makefile

@@ -9,8 +9,9 @@ ELF=$(addprefix build/,$(TESTS))
 ELF32=$(addsuffix 32,$(ELF))
 ELF64=$(addsuffix 64,$(ELF))
 
-RISCVCC64=riscv64-unknown-elf-gcc -march=rv64im -mabi=lp64 -static -nostdlib -nostartfiles -mcmodel=medany
-RISCVCC32=riscv32-unknown-elf-gcc -march=rv32im -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany
+# RISCVCC64=riscv64-unknown-elf-gcc -march=rv64ima -mabi=lp64  -static -nostdlib -nostartfiles -mcmodel=medany
+RISCVCC64=riscv64-unknown-linux-gnu-gcc -march=rv64ima -mabi=lp64  -static -nostdlib -nostartfiles -mcmodel=medany
+RISCVCC32=riscv32-unknown-elf-gcc -march=rv32ima -mabi=ilp32 -static -nostdlib -nostartfiles -mcmodel=medany
 
 build32: $(ELF32)
 

Tests/asm/asm-source-tests/rv64ua/Makefrag

@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv64ua tests
+#-----------------------------------------------------------------------
+
+rv64ua_sc_tests = \
+	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+	lrsc \
+
+rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
+rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
+
+spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)

Tests/asm/asm-source-tests/rv64ua/amoadd_d.S

@@ -0,0 +1,47 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoadd.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff7ffff800, \
+    amoadd.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0

Tests/asm/asm-source-tests/rv64ua/amoadd_w.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoadd.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x000000007ffff800, \
+    li  a1, 0xffffffff80000000; \
+    amoadd.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+    .bss
+    .align 3
+amo_operand:
+    .dword 0

Tests/asm/asm-source-tests/rv64ua/amoand_d.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoand.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    amoand.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0

Tests/asm/asm-source-tests/rv64ua/amoand_w.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoand.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    amoand.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0

Tests/asm/asm-source-tests/rv64ua/amomax_d.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sd x0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0

Tests/asm/asm-source-tests/rv64ua/amomax_w.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sw x0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0